同步时序逻辑电路设计步骤研究

通过对时序逻辑电路设计部分教学过程的设计步骤分析研究,强化了原始状态的确定在设计过程中的重要性,在清晰设计思路,强化时序逻辑电路经典的设计方法的同时,补充了与实践应用相关的设计实例,完善了时序逻辑电路的设计步骤。     

异步时序逻辑电路的设计方法探讨

在传统的同步时序电路设计方法的基础上,提出了一种新的异步时序电路的设计方法。该方法直接从时序电路的时序波形图,获得触发器的触发脉冲;根据时钟信号作用下引起的状态转换,填写次态卡诺图。其特点是原理简单,易于理解,使设计更加直观清楚。     

时序逻辑电路ASIC化PLA模型设计法（一）

专用可编程集成电路（ASICApplicationSpecificIntegratedCircuit）是速度快、集成度高、用户可编程的逻辑器件。近几年，在数字系统和计算机外围接口电路设计中ASIC得到了广泛的应用。本文给出的用PLA模型设计时序逻辑电路的方法不同于传统的时序电路设计方法，更适用于ASIC实现时序逻辑电路。文中给出了经过仿真和验证、功能正确的设计实例电路。     

原始状态在时序逻辑电路设计中的应用研究

原始状态的确定对于时序逻辑电路的设计而言十分重要,本文通过对设计实例设计过程中原始状态的分析和确定,完善了时序逻辑电路的设计步骤,使时序逻辑电路的设计思路更加清晰。     

时序逻辑电路设计法在数字图像显示控制器中的应用

１概述数字时序电路广泛应用于家用电器、工业电器等,几乎在电子新产品开发过程中都会碰到数字时序电路的逻辑设计问题。数字时序电路逻辑设计常用的设计步骤如图１所示。其中过程１,２,３难度最大,特别是输人、输出。状态反馈等信号比较多时,状态图、状态表变得十分庞杂,稍有疏忽就会造成错误［１］。另外用这种方法设计过程中很难验证所画所建的状态图、表的正确性。只有当电路实现完成后才能进行功能验证,所以设计周期长、损耗大。为了克服上述缺点,提高首次设计的成功率,文中提出一种直观。高效时序电路逻辑设计法,并通过设计…     

一种基于时序逻辑电路的延时开关设计

时序逻辑电路设计是《数字电子技术》课程中一个难度大、综合性高的部分,它综合了组合逻辑电路和时序逻辑电路的内容。在进行状态机设计时,随着输入逻辑变量的增加,状态数目将呈指数倍急剧增加,这会使整个设计变得复杂且容易出错。以一个延时开关控制器的设计为例,提出了一种状态机输入变量简化的方法,降低了设计过程的复杂程度。     

时序逻辑电路失效分析

利用液晶热点定位和电压衬度像等技术手段,准确定位了一时序逻辑电路的失效部位,结合电路原理分析以及芯片版图,详细解释了器件失效模式与失效现象的关系,并对其失效原因进行了实验验证.结果显示,电压衬度技术可以直观地显示逻辑电路内部某点的逻辑状态,在失效定位以及失效模式确认方面起重要作用;时序逻辑电路失效后存在电势竞争现象,本失效案例表明,当电路中某点出现"1"和"0"的电势竞争时,该点表现为"1".     

用数字集成电路实现时序逻辑电路的功能

介绍了时序逻辑电路的概念以及用ＣＤ４０２８数字集成电路设计时序电路的实例。     

基于数据选择器和D触发器的多输入时序电路设计

为了探索多输入时序逻辑电路的简便实现方法,介绍了基于数据选择器和D触发器的多输入时序逻辑电路设计技术。即将D触发器和数据选择器进行组合,用触发器的现态作为数据选择器选择输入变量、数据选择器的输出函数作为触发器的D输入信号,构成既有存储功能又有数据选择功能的多输入端时序网络。由触发器的现态选择输入变量、所选择的输入变量决定触发器的次态转换方向。该方法适合实现互斥多变量时序逻辑电路,且在设计过程中不需要进行函数化简。     

触发器的广义特性方程及其应用

本文建立了触发器的广义特性方程，并介绍了它在时序逻辑电路分析中的应用     

探讨计数器设计的授课思路与方法

根据作者多年来的教学实践经验,探讨了数字逻辑电路中二进制、十进制和任意进制计数器设计方面的一些授课思路与方法。     

基于时钟设计的异步时序逻辑电路设计法

基于时钟设计的异步时序逻辑电路设计法,根据电路状态转换规律,立足电路中各位触发器时钟设计,使电路完成所要求的逻辑功能,从而避免了求解电路状态方程,驱动方程。     

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts. Hiroyuki Yotsuyanagi received his B.E., M.E. and Ph.D degrees from Osaka University, in 1993, 1995 and 1998, respectively. In 1998 he joined the Department of Electrical and Electronic Engineering, the University of Tokushima, where he is currently an Associate Professor. His research interest includes test synthesis for sequential circuits and current testing for CMOS ICs. He is a member of the IEICE and the IEEE. Toshimasa Kuchii received B.E., M.E., and Ph.D. degrees in Electrical and Electronic Engineering from the University of Tokushima in 1994, 1996, and 1999, respectively. He is currently a DFT engineer at Sharp Corporation. His research interests are DFT methodologies for SoC devices, PLL jitter testing, and DFT for image sensor devices. Shigeki Nishikawa received B.E. in the Department of Information and Behavioral Sciences from Hiroshima University in 1980. He is currently a manager of LSI test engineering department at Sharp Corporation. His research interests are DFT, DFM and the total solution of testing technologies in the CAE tools. Masaki Hashizume received his B.E. and M.E. degrees in electrical engineering from the Univ. of Tokushima and Dr.E. degree from Kyoto Univ., in 1978, 1980 and 1993, respectively. He is currently a Professor of the Department of Electrical and Electronic Engineering, Faculty of Engineering, the Univ. of Tokushima. His research interests are logic synthesis and supply current testing of logic circuits. Kozo Kinoshita received B.E., M.E., and Ph.D. in Communication Engineering from Osaka University in 1959, 1961, and 1964, respectively. From 1964 to 1966 he was an Assistant Professor and from 1967 to 1977, an Associate Professor of Electronic Engineering at Osaka University, Osaka, Japan. From 1978 to 1989, he was a Professor in the Department of Information and Behavioral Sciences, Hiroshima University, Hiroshima, Japan. From 1989 to 2000, he again joined Osaka University as a Professor in the Department of Applied Physics, and is enumerates professor of Osaka University. Since April 2000, he has been a professor at Faculty of Informatics, Osaka Gakuin University, and is the Dean of Informatics. His fields of interest are test generation, fault diagnosis, memory testing, current testing, crosstalk testing, compact testing and testable design for logic circuits. He organized a series of Asian Test Symposium and was the Group Chair of Asian and Pacific Activities in Test Technology Technical Council of IEEE Computer Society until 2002. Prof. Kinoshita is IEEE Life Fellow, IEICE Fellow and a member of the Institute of Information Processing of Japan. He was a member of the editorial board of JETTA until 2000.     

米里电路设计中的状态化简问题

本文讨论了米里电路设计中的状态化简问题,指出状态化简后的电路有可能不能正常工作,给出了状态化简的适用条件和使用注意事项。     

时序电路的形式化证明

对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述.本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用Tempura的程序B表示对该电路的特性描述.公式B（∈）P引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式.这样,一旦证明了B（∈）P,就能证明实现满足规格描述.最后,给出了一个例子来说明此证明方法.     

串行数据检测器的设计

分析了时序逻辑电路设计中的状态化简问题,指出了状态化简不会改变电路的逻辑功能,不可能使电路产生错误输出。讨论了串行数据检测器的米里型电路设计和摩尔型电路设计,提出了一种在输入数据稳定的区段进行检测、确定电路状态,在输入数据改换为下一位时输出状态信息,确保系统正常工作的米里型电路设计方法,这种方法对米里型电路的设计有通用性。