STATE VERIFICATION FOR SYNCHRONOUS CIRCUITS

This paper presents the techniques of implicit traversing and state verification for sequential finite state machines(FSMs) based of on the state collapsing of state transition graph(STG). The problems of state designing are described. In order to achieve high state enumeration coverage, heuristic knowledge is proposed.     

Timing circuits for RSFQ digital systems

A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm². The most complex clock controller generates trains of 2²⁴ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6×10^-5 . The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz     

Multivalued dynamic circuits

A new family of multivalued logic circuits is presented. These circuits exhibit some appealing features: they are the first MV dynamic operators reported in the literature, they implement the Vranesic-Smith-Lee algebra (which is specially suited for arithmetic operations), and their performance has been found to be similar to binary counterparts by simulation.     

Analysis of blocking dynamic circuits

In order for dynamic circuits to operate correctly, their inputs must be monotonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is negative. With blocking dynamic circuits, cascading low-skew dynamic gates allows each dynamic gate to tolerate a degraded input level. The larger noise margin provides greater flexibility with the delay versus noise margin tradeoff (i.e., the circuit robustness versus speed tradeoff). This paper generalizes blocking dynamic circuits and provides a systematic approach for assigning clock phases, given delay and noise margin constraints. Using this framework, one can analyze any logic network consisting of blocking dynamic circuits.     

Design and synthesis of dynamic circuits

Dynamic circuits are widely used in today's high-performance microprocessors for obtaining timing goals that are not possible using static CMOS circuits. Currently, no commercial tools are able to synthesize dynamic circuits and therefore their design is either completely done by hand or aided by proprietary in-house design tools. This paper describes methodologies and tools for the design and synthesis of dynamic circuits, including general monotonic circuits, which consist of alternating low-skew and high-skew logic gates that may both contain functionality. Synthesis results show standard domino, dynamic-static domino, monotonic static CMOS, zipper CMOS, and footless domino and clock-delayed domino circuits to have average speed improvements of 1.57, 1.66, 1.67, 1.47, 1.71, and 1.60 times over static CMOS, respectively.     

Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

Specification, synthesis, and verification of hazard-free asynchronous circuits

This article describes three aspects of asynchronous design from a Petri-net specification called asignal transition graph (STG). First, we show that the STG defined by Chu [1] is too restrictive for specifying general asynchronous behavior and propose extensions to the STG which allow for more general and compact representation. Second, we show that syntactic constraints on STGs are not sufficient to guarantee hazard-free implementations under the unbounded gate delay model, and present techniques to synthesize two-level implementations which are hazard-free under the multiple signal change condition. To remove all hazards under the multiple signal change condition, the initial specification may need to be modified. Finally, we show that behavior containment test using the event coordination model [2] is a powerful tool for the formal verification of asynchronous circuits. This verification method can provide sanity checks for all synthesis methods that use the unbounded gate delay model, and provides a mechanism for designers to validate some manual gate-level changes to the final design.     

Current testing in dynamic CMOS circuits

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.     

Realistic scalability of noise in dynamic circuits

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.     

Neural-based dynamic modeling of nonlinear microwave circuits

A neural network formulation for modeling nonlinear microwave circuits is achieved in the most desirable format, i.e., continuous time-domain dynamic system format. The proposed dynamic neural network (DNN) model can be developed directly from input-output data without having to rely on internal details of the circuit. An algorithm is developed to train the model with time or frequency domain information. Efficient representations of the model are proposed for convenient incorporation of the DNN into high-level circuit simulation. Compared to existing neural-based methods, the DNN retains or enhances the neural modeling speed and accuracy capabilities, and provides additional flexibility in handling diverse needs of nonlinear microwave simulation, e.g., time- and frequency-domain applications, single-tone and multitone simulations. Examples of dynamic modeling of amplifiers, mixer, and their use in system simulation are presented.     

A static verification approach for architectural integration of mixed-signal integrated circuits

In this paper we present a static method for verifying the proper integration of analog and mixed-signal macroblocks into an integrated circuit. We consider the problem in a setting where there is no golden reference for verifying the validity of the interconnections between the blocks. The proposed verification methodology relies on an abstract modeling of the functional behavior of the blocks and a set of consistency criteria defined over the composition of these abstract models. A new formalism called mode sequence chart (MSeqC) has been presented for capturing the behavior of the blocks at a level of abstraction that is suitable for interconnection verification. We present rules to compose the MSeqCs of each block in an integrated design and present three criteria that indicate possible interconnection faults. We present a tool called AMS-IV (AMS-interconnection verification) that takes the design netlist as input, the MSeqC model of each design block as reference, and tests the three criteria.     

Static and dynamic noise margins of logic circuits

Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example.     

分形分抗逼近电路零极点的数值求解与验证

随着分抗逼近电路理论的高速发展,如何求解分抗电路的零极点是研究的重点问题之一。利用常规友矩阵求解分抗逼近电路的零极点,出现虚根而得不到正确的解。为了解决这个问题,基于分抗逼近电路的迭代电路和迭代矩阵,利用矩阵实验室(MATLAB)中的"solve"和"roots"函数实现分抗逼近电路归一化零极点的数值求解,并比较两者的精确度和运算速度。对求得的解进行直接验证和间接验证。仿真结果表明,该方法实现了分抗逼近电路零极点的准确求解,对于分抗逼近电路的分析具有指导性意义。     

MOS capacitor pull-up circuits for high-speed dynamic logic

The use of an MOS capacitor as an integrated load element in dynamic inverters is reviewed and a particular approach (direct cascading) to its application is demonstrated. Experimental n-channel capacitor pull-up shift registers are demonstrated to operate with multiphase clocks at frequencies up to 34.5 MHz, which is about twice the limit of conventional MOS dynamic circuits fabricated with the same Si-gate process. A substrate bias is used to eliminate minority carrier injection which was previously reported to limit the high frequency performance. Possible applications of this circuit are discussed.     

Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection circuits

Experimental analysis of the dynamic characteristics of various silicon-controlled rectifier (SCR)-type ESD protection circuits at various temperatures has been carried out. These circuits include MOSFET-trigger SCR (MTSCR), diode-chain-trigger SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The static trigger voltage increases with temperature if the SCR uses the breakdown trigger mechanism, otherwise it decreases with temperature. The peak pad voltages for the MTSCR and DCTSCR subjected to a pulse-like ESD stress decrease with increasing temperature, while those of GCSCR and LVTSCR are relatively insensitive to temperature.     

Analysis of dynamic characteristics of process of designing analogue circuits

The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system’s properties it is suggested to use the concept of Lyapunov’s function for a dynamic system. Various forms of Lyapunov’s function are suggested. Analyzing the behavior of Lyapunov’s function and its first derivative allowed to determine significant correlation between this function’s properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov’s function for the process of designing the circuit.     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FETlogic

Two-phase dynamic FET logic (TDFL) gates are used in GaAs MESFET MSI circuits to implement very low power 4-b ripple carry adders and a variable modulus (2 to 31) prescaler. Operation of the adders is demonstrated at 500 MHz with an associated power dissipation of less than 1.0 mW and at 750 MHz with P_d=1.7 mW. The prescaler, which contains 166 TDFL gates and 79 static gates, is shown to operate up to 850 MHz with an associated power dissipation of 9.2 mW from its 1.0-V supply. The operation of the adders and prescalers demonstrates the use of three- and four-input TDFL gates and a completely dynamic TDFL XNOR gate. The TDFL gates in these circuits dissipate only from 14 to 20 nW/MHz