ABB i-bus EIB智能楼宇环境控制系统的应用

本文简要介绍了ABB i—bus (EIB智能楼宇环境控制系统的应用场合，并结合青岛移动通信办公大楼的工程实例详细介绍了i—bus系统在智能楼宇中的应用方案。最后，根据试验数据给出了i—bus在某公司应用的节能分析报告，并结合成都双流机场项目分析了智能楼宇采用i—bus系统的节能效果和投资回报。     

Reconfigurable Optical Bus and Performance Optimization

With the advent of optical fiber and other advanced technologies in solid state,pipelining signals at the wire(or transmission line)level has becomr possible.This has,in turn,made the slotted bus a potential candidate for interconnection networks(IN)for tightly coupled multiprocessor systems.However,a bus an provide only limited bandwidth.Though slotted bus can provide considerably more bandwith in comparison to the traditional non-slotted bus,it is not enough for fine-grain parallel applications run on the shared-memory systems.One well known method to increase the effective bandwidth of a slotted bus in the LAN/MAN environment is to reuse the bandwwidth by reusing slots.However,in a tightly coupled environment reusing slots is not a lucrative option because the significant buffering needs arising from slot reuse will introduce intolerable delay.In this paper we propose a methodology to reuse part of the bandwith available from temporal and spectral bandwidth expansion with none of minimum buffering delay,resulting in significant performance improvement in both the effective throughput and response time(communication latency).The proposed method entails the design and analysis of a re-configurable bus structure with both temporal and spectral bandwidth expansion and a polynomial time algorithm for optimal configurations for given traffic conditionslWe have compared the performance of our reconfigured bus with that of the traditional slotted bus for uniform and localized traffic pattern and founr that the reconfigured bus outperforms the traditional slotted bus substantially in many practical scenarios.     

Throughput models of CSMA network with stations uniformly distributed along the bus

The distribution of station locations in a CSMA network can have significant effect onnetwork throughput. In this paper, we develop an analytic model for unslotted, non-persistentCSMA bus network where the stations are uniformly distributed along the bus. We derive aclosod form expression for throughput approximation, and discuss the fairness of CSMAprotocol using the bus topology. Analytic and simulation results are presented and compared.     

一款实用的仿真软件—proteus6．7（二）

例2．把74LS373改成．bus接口我们可以修改Proteus中的元件,比如把74LS373改成．bus接口的,有两种实现方案。     

Designing of CAN Network Analyzer Based on SJA1000

Controller Area Network(CAN) bus has become increasingly important in numerous areas.It is meaningful to ensure its proper functioning.With controller SJA1000 as the core component,the thesis designs a CAN network analysis device, for on-site monitoring CAN bus operating conditions.The test result indicates that when accessed to the network,the device doesn’t affect the communication between CAN buses, just monitors the transferring messages and displays bus -error, baud-rate and so on.Such important parameters of CAN-bus are helpful to realize network disaster recovery.     

Implementable strategy research of brake energy recovery based on dynamic programming algorithm for a parallel hydraulic hybrid bus

The purpose of this paper is to develop an implementable strategy of brake energy recovery for a parallel hydraulic hybrid bus. Based on brake process analysis, a dynamic programming algorithm of brake energy recovery is established. And then an implementable strategy of brake energy recovery is proposed by the constraint variable trajectories analysis of the dynamic programming algorithm in the typical urban bus cycle. The simulation results indicate the brake energy recovery efficiency of the accumulator can reach 60% in the dynamic programming algorithm. And the hydraulic hybrid system can output braking torque as much as possible.Moreover, the accumulator has almost equal efficiency of brake energy recovery between the implementable strategy and the dynamic programming algorithm. Therefore, the implementable strategy is very effective in improving the efficiency of brake energy recovery.The road tests show the fuel economy of the hydraulic hybrid bus improves by 22.6% compared with the conventional bus.     

Bus-Switch Encoding for Power Optimization of Address Bus

This paper presents a novel encoding technique to minimize the switch activities on the highly capacitive memory address bus so as to reduce power dissipation of bus. This technique is based on the temporal locality and spatial locality of instruction address. The experimental results based on an instruction set simulator and SPEC2000 benchmarks show that the presented encoding technique can reduce signal transitions on the address bus by 83.8%, and the actual overhead of the encoder circuit is estimated after encoder has been designed and synthesized with 0.18-μm CMOS technology. The results show that our technique well outperforms specialized low-power encoding schemes presented in the past.     

一种基于CPLD的I／O总线驱动液晶显示的方法

The paper discusses a new kind of driving the LCD via I/O bus using CPLD and realizing the precise I/O control timing sequence by establishing the corresponding Verilog-HDL model. The results of application show that this solution can not only solve the matching of low-speed device with high-speed bus but also provide the display in-terface during the motherboard debugging process, and also prove that the whole system is reliable and stable.     

Distributed Economic MPC for Synergetic Regulation of the Voltage of an Island DC Micro-Grid

In this paper, distributed model predictive control(DMPC) for island DC micro-grids(MG) with wind/photovoltaic(PV)/battery power is proposed, which coordinates all distributed generations(DG) to stabilize the bus voltage together with the insurance of having computational efficiency under a real-time requirement. Based on the feedback of the bus voltage, the deviation of the current is dispatched to each DG according to cost over the prediction horizon. Moreover, to avoid the excessive fluctuati...     

一种新型的单片机系统总线——MCU BUS

单片机系统的模块化设计对用户和制造商具有十分重要的意义,而目前在计算机应用系统中使用的总线,都不适合用单片机作它的主处理机.因此,单片机总线的设计受到普遍的关注.在单片机系统模块化研制过程中设计出的MCU bus单片机系统总线适应性强、结构合理、体积小,适合单片机系统的模块化设计和嵌入式应用.文中主要介绍 MCU bus的特点及其规范.     

基于iCAN协议的CAN-bus分布式控制系统

从建立一个分布式控制系统的角度，探讨CAN—bus网络的应用，以及iCAN协议的制定，这是本文的主要内容。     

凌华科技推出4通道16位800 kS／s高速同步数据采集卡

2006年6月9日，凌华科技推出16位高分辨率、4通道同步的PXI平台数据采集卡PXI-2016，采样频率每通道最高可达800 kS／s，主要针对高速采样且在多通道间同步数据采集上有特殊需求的应用，如工厂自动化、超声、声音信号及生物医疗等。同样规格，亦同时提供PCI总线的DAQ-2016。无论是DAQ-2016或PXI-2016，都可分别通过SSI bus或是PXI trigger bus达到不同模块间更多通道同步的应用。     

Using Tensilica Xtensa configures a dual-core processor based-on SoC

In this paper, we proposed a multi-core processor, which is based on system-on-chip （SoC） architecture and established by configurable processor via Tensilica Xtensa LX2. The purpose of this paper is to describe the heterogeneous configurable dual-core processor, in which one core is responsible host operating control for the system and the other is as an extension of digital signal processing applications. However, the designed core not only owns its local memory, but also shares a common data-memory. We also put virtual memory in this proposed processors, this addition memory allows processor easily to handle a more complex application programs while two cores are able to share a unified data-memory in different kinds tasks, simultaneously. The advantages of the proposed structure can avoid and reduce many hard-wired of memory and interface respectively. For bus managing, a single bus as interface is proved. In this bus system an arbitration mechanism is added to handle the communication between cores and to distribute the priority of access request, in order to ensure that those cores operation under synchronously.     

S—100696与IEEE796系统总线性能比较及其与Z8001微处理机的配合

一、绪言微计算机的系统结构采用面向总线的设计后,带来了简化硬软件的设计和系统结构,系统扩充性好,系统更新性好的优点。微计算机的总线可分为三种: 局部总线(或片总线)(local bus):连接微处理机片子,存贮器片子,外围接口片。在电路器件间建立标准通迅接口,如:ZCI总线(Z总线)即属于局部总线。系统内总线(intrasystem bus),简称“系统总线”。是插板级总线。它提供了构成微机系统插件板间的标     

POTENTIAL: A highly adaptive core of parallel database system

POTENTIAL is a virtual database machine based on general computing platforms,especially parllel computing platforms.It provides a complete solution to high-performance database systems by a ‘virtual processor virtual data bus virtual memory‘ architecture.Virtual processors manage all CPU resources in the system,on which various operations are running.Virtual data bus is responsible for the management of data transmission between associated operations.which forms the higes of the entire system.Virtual memory provides efficient data storage and buffering mechanisms that conform to data reference behaviors in database systems.The architecture of POTENTIAL is very clear and has many good features,including high efficiency,high scalability,high extensibility,high portability,etc.     

Development of an Active SERCOS Card

SERCOS is a data exchange protocol between CNC -controller and digital drives. The author developed an Active SERCOS Card based on PC ISA bus. With this card, we can control digital drives with SERCOS interfaces without any detailed knowledge of SERCOS. This paper introduces the hardware and software architectures of the card.     

A Comparative Analysis of Different Arbitration Protocols for Multiple-Bus Multiprocessors

Earlier performance studies of multiple-bus multiprocessor systems assume a random selection of competing requests for bus assignment and ignore the effects of realistic bus arbitraion schemes on the performance of such systems.In this paper,we present performance analysis of the multiple-bus systems with different arbitration protocols.The priority protocols considered are random selection,fixed priority,rotating priority,round-robin and FIFO.Analytical models are developed for each of these five different priority protocols.Each of our analyses models exactly the behavior of the corresponding priority protocol with little computation cost.The analytical models are validated through extensive simulations and are them used to carry out performance analysis and comparison of different priority protocols.Numerical results obtained from our models show that the round-robin protocol performs the best amont the five protocols in the system with a few buses.     

Extracting DC bus current information for optimal phase correction and current ripple in sensorless brushless DC motor drive

Brushless DC motor （BLDCM） sensorless driving technology is becoming increasingly established. However, op- timal phase correction still relies on complex calculations or algorithms. In finding the correct commutation point, the problem of phase lag is introduced. In this paper, we extract DC bus current information for auto-calibrating the phase shift to obtain the correct commutation point and optimize the control ofBLDC sensorless driving. As we capture only DC bus current information, the original shunt resistor is used in the BLDCM driver and there is no need to add further current sensor components. Software processing using only simple arithmetic operations successfully accomplishes the phase correction. Experimental results show that the proposed method can operate accurately and stably at low or high speed, with light or heavy load, and is suitable for practical applications. This approach will not increase cost but will achieve the best performance/cost ratio and meet market expectations.     

利用LPC2300系列ARM芯片的I~2S实现WAV文件播放

I2S(Inter-IC Sound Bus,集成电路内置音频总线)是工业领域或嵌入式系统领域常用的音频总线之一,它只处理音频数据,而其它信号如编码、控制等单独传送.使用I2S总线bus和支持该接口的编解码芯片连接,从而构建一个嵌入式音频系统.