一种SET/CMOS混合器件模型的建立及特性分析

本文基于一种单电子晶体管数学模型（改进的MIB模型），实现其SPICE宏模型。提出一种改进型SET／CMOS混合器件模型，并用SPICE对其I-V特性进行了仿真验证，仿真结果证实了电流与电压具有线性关系。此混合模型的线性电流区可以在积分器以及滤波器电路中得到应用。     

结深对65nm体硅CMOS晶体管单粒子瞬态脉冲的影响

使用TCAD模拟工具,分析了纳米工艺下N+-N结、P+-P结和PN结深度的变化对PMOS以及NMOS单粒子瞬态(SET)脉冲宽度的影响,并考虑了电压温度变化下结深对晶体管单粒子瞬态的影响程度。结果表明,N+-N结的变化对PMOS晶体管单粒子瞬态脉冲宽度的影响最为显著。同时,还分析出N+-N、P+-P结在不同电压下的差异性较为明显,PN结在不同温度下的差异性较为显著。     

CMOS离子敏场效应管SPICE模型

完全用CMOS工艺实现离子敏场效应型晶体管(ISFET)成为可能,这种ISFET的栅极结构是由绝缘体、多晶硅、金属层叠起来,称之为多层栅结构。从ISFET的传感机理出发,通过分析金属氧化物场效应晶体管(MOSFET)阈值电压的原理,利用通用电路模拟程序(SPICE)建立了这种多层栅结构ISFET的物理模型,并对其静态输入输出特性进行仿真,仿真结果和试验数据基本相符。     

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Heavy ion experiments were performed on D flip-flop （DFF） and TMR flip-flop （TMRFF） fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU cross- section compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2~ harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.     

A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique~ we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.     

Constitutive relations for nonlinear modeling of Si/SiGe HBTs using an ANN model

In this article, we demonstrate how the constitutive relations for the nonlinear modeling of hetro‐junction bipolar transistors (HBTs) can be based on an artificial neural network (ANN) model representation.. The model is implemented using a commercial microwave simulator, and has been validated by DC and nonlinear measurements. Excellent agreement is obtained as compared with the results of the DC measurements, and the model predicts well the higher‐order harmonics in a single tone test.. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.