Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Modeling the partition of noise from the gate-tunneling current in MOSFETs

Expressions for the spectral densities of the gate/source and gate/drain noise currents caused by current flow through the gate oxide of MOSFETs are derived. It is shown that these noise currents can also be expressed in terms of equivalent gate and drain noise currents, and by linearizing the position dependence of the gate current density, simple analytic expressions for these equivalent noise currents and their correlation are obtained in terms of the total gate current and the drain/source partition ratio. It is also shown that the predictions of this simple theory are consistent with published experimental data and results from numerical simulations.     

Off-state instabilities in thermally nitrided-oxide n-MOSFETs

The significant off-stage gate current of nitrided-oxide n-MOSFETs can be attributed to severe hot-hole injection into the gate oxide during band-to-band (B-B) tunneling due to a nitridation-induced lowering of the barrier height for hole injection. Some of the injected holes are even trapped in the gate oxide above the deep-depletion layer of the drain and thus decrease the gate-induced drain leakage (GIDL) current. A subsequent hot-electron injection into the gate oxide can neutralize these trapped holes and make the reduced GIDL current recover, even increase beyond the original value. The proposed mechanism of the GIDL degradation and recovery behaviors can be confirmed by the observed change in the ratio of the substrate to source currents, as well as by the field-distribution analysis of the gate oxide under stressing     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.     

A lifetime prediction method for hot-carrier degradation insurface-channel p-MOS devices

Hot carrier degradation of p-MOS devices at low gate voltages (V_g<V_d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Study of MOS gate dielectric breakdown due to drain avalanche breakdown

This work reports the effects of drain impact ionization injection on the gate dielectric breakdown. Results show that due to the high energy hot carrier injection, the gate oxide can break down twice at a low oxide electric field (<1.2 MV/cm). The first breakdown occurs simultaneously with the drain avalanche breakdown whereas the second breakdown occurs beyond the drain breakdown. It is further identified that the first gate oxide breakdown is governed by the thermionic emission of hot electrons at low oxide fields (<1.0 MV/cm) and by the scattering processes at higher oxide fields. The second breakdown is attributed to the Fowler–Nordheim (F–N) tunneling.     

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO2energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to2 times 10^{-4}A/cm². The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.     

Negative differential conductivity and isothermal drain breakdownof the GaAs MESFET

Electrical breakdown in GaAs MESFET's is simulated by two-dimensional (2-D) quasi hydrodynamic isothermal model with two types of carriers and “mixed” boundary conditions on the contacts-fixed drain current and fixed gate bias. It was demonstrated, that when some maximum drain voltage is reached the MESFET's differential conductivity becomes negative at every gate bias. The negative differential conductivity (NDC) is caused by the electric field reconstruction in the buffer by the injected carrier space charge. It is shown that the suggested breakdown model corresponds to the experimentally observed properties of the drain breakdown of the GaAs MESFET. The instantaneous burnout of the GaAs MESFET at the drain breakdown is explained by the uncontrollable drain current increase due to the NDC formation     

Effect of hot-carrier injection on n- and pMOSFET gate oxideintegrity

N- and pMOSFETs with 9-nm gate oxide are compared. Injected hot holes are about 100 times as effective as electrons at 10.5 MV/cm of oxide field in causing oxide breakdown. Gate current in nMOSFETs under stress conditions is due to holes and electrons. The gate current in pMOSFETs is about 1000 times as large, but solely due to electrons. PMOSFETs can tolerate 1000 times more charge injection than nMOSFETs, but not more drain current stress     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs