Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.     

Design of an FPGA based DPLL with fuzzy logic controllable loop filters with application customization capability

The carrier recovery loops are important in carrier tracking approaches particularly in the presence of high dynamic stress on user receivers and noisy environment applications. The precise carrier tracking techniques are proposed in systems that are sensitive to carrier mismatches, such as terrestrial or satellite tracking systems. The fading phenomenon, phase and frequency step changes and high user dynamics are currently most important challenges in the development of robust carrier tracking systems. In this work, a novel Digital Phase Locked Loop (DPLL) is proposed using type-2 fuzzy logic controller to improve noise immunity and handling user dynamic in digital receivers with application customization capability. Due to fast and accurate decision-making by proposed fuzzy logic controller, optimal loop filter coefficients are generated for DPLL. The proposed DPLL is simulated with Xilinx System Generator Software and can be implemented on FPGA. In comparison to traditional approaches, proposed new DPLL shows better performance in response to phase step, frequency step and frequency ramp signals with acceptable settling time alongside minimum complexity in implementation and customization.     

Ballistic transport in semiconductor at low temperatures for low-power high-speed logic

At low temperatures, a mean free path of electrons in semiconductors may exceed device dimensions. Current-voltage characteristics, potentials, electrical field, and carrier distributions are calculated for a two-terminal device under such conditions when the electron transport is ballistic. Current-voltage characteristics of a "ballistic" FET are analyzed using an approach similar to the Shockley model. It is shown that very high drift velocities can be obtained at low voltages leading to high speed and low power consumption in possible applications in logic circuits. For example, GaAs logic devices with characteristic dimensions about a micrometer or less at 77 K will be comparable with or better than Josephson tunneling logic gates.     

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.     

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

Attojoule MOSFET logic devices using low voltage swings and low temperature

Previous estimates of the performance limits of MOSFET logic devices, including the possibility of low temperature operation, have used the conventional static electrical behavior as a starting point. Typically, such studies conclude that the minimum voltage swing is ～ 200 mV, leading to practical limits on power dissipation and switching speed that prohibit the combination of very low-power dissipation and very high speed achieved in Josephson junction logic. At such low voltages, the device behavior becomes very sensitive to fabrication, making high yields difficult. Here we consider the conditions which must be met to achieve high speed and low power VLSI logic devices through voltage swings ～ 25 mV. Dynamic logic through bulk conduction devices operating at T ? 30K represents the major requirements. At such low temperatures, nonequilibrium processes provide a new basis for device action, and a novel relaxation mode MOSFET operating under carrier freezeout conditions is suggested as a possible low-voltage swing logic switch with power-delay products in the attojoule range.     

Analytical approach of developing the expression of output of all-optical frequency encoded different logical units and a way-out to implement the logic gates

To implement different all optical logic operations, encoding/decoding of optical signal is a very important issue. Since now there are so many types of optical signal encoding and decoding techniques have been adopted, such as intensity encoding, polarization encoding, phase encoding, symbolic substitution technique etc. All these existing techniques have their own limitations. In this context one may mention the frequency encoding/decoding technique. The basic inherent advantage of frequency encoding technique over all other existing techniques is that as the frequency of a signal is the fundamental character of it, it always preserves its identity throughout the communication of the signal, irrespective of reflection, refraction attenuation etc. Again, different optical signal has different distinct frequency which may be encoded as a distinct state of a logic system to represent the information. Adopting this technique it is possible to implement binary logic system as well as higher order logic system such as tristate logic, quaternary logic system etc. The major advantages of multivalued logic system over Boolean logic system are that in multivalued logic system the states of information is very more and as result information storage capacity is high. Again in multivalued logic system carry free and borrow free operation can be implemented which is less time consuming and therefore speed of operation is very fast. We have already developed methods of implementation of different all-optical frequency encoded logic as well as different optical processor. In this communication we propose an analytical approach to develop the expression of the outputs of frequency encoded different binary logic expression in terms of input frequencies from the stand point of basic laws of reflection, transmission and frequency conversion property of optical devices and of course mention the way-out to implement these logic operations.     

一种宽频压控振荡器及高速双模预分频器的设计与实现

针对射频无线收发机的需求,利用开关电容阵列和多个VOD核的结构设计了一个分段线性超宽频压控振荡器(VCO).采用全电流模逻辑(CML)结构的双模预分频器能满足振荡器最高频率输出的要求.基于IBM 0.35SiGe BiCMOS工艺的流片测试结果表明,电源电压为2.8V时,该压控振荡器的频率能够覆盖2.75～5.73GHz的频段,调频灵敏度约为100MHz/V,在偏离中心频率1MHz处,单边带相位噪声最佳值达到了-120.32 dBc/Hz,预分频器后仿最高工作频率达9.6GHz,两部分核心总工作电流为10mA.     

Microwave Frequency Translator

A stepped phase-shift approach, employing semiconductor switching techniques in waveguide, is used to achieve frequency translation at microwave frequencies. Stepped phase shift is employed to approximate a continuous or ideal sawtooth phase shift. It has been shown by Fourier analysis that three is the minimum number of phase steps required to achieve frequency translation with suppression of the carrier and first symmetrical sideband. A tunable device using microwave switching diodes in a single port Y junction is described. The diodes progressively switch three lenths of waveguide into the circuit establishing three phase steps. A ferrite circulator is used to create a two port device and a modulator supplies proper diode biases and switching logic. Carrier suppression of greater than 30 dB and first symmetrical sideband suppression of greater than 20 dB was observed; other sideband amplitudes are predictable. A conversion efficiency of -6 dB including the circulator loss was measured and the bandwidth for 20 dB carrier suppression varies from almost one per cent to three per cent, depending on other suppression criteria.     

A 20-ps Si bipolar IC using advanced super self-aligned processtechnology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector     

Radio Frequency Pulsewidth Modulation

The width of a train of square pulses can be varied to produce a modulated carrier at the pulse repetition frequency. When the pulse train is generated by switching (class D) transistors, highefficiency operation is possible. The efficiency of this type of amplifier can be significantly higher than that of conventional pulsewidth modulation amplifiers, since the switching rate is reduced. In addition, the spectrum of a bipolar pulse train so modulated has the highly desirable property of all spurious products being band limited near the odd harmonics of the carrier.     

Superconductor digital RF development for software radio

We review a new “direct digitization” approach for “digital RF” architectures for software radio. Although direct digitization usually implies the simultaneous digitization of all channels in a particular band at a downconverted IF, we use this term to refer exclusively to the direct digitization of all bands, from near DC to RF. Furthermore, we present results on band selection and digitization of RF signals directly at the carrier frequency with high resolution. These novel approaches are enabled by a superconductor analog-to-digital converter technology using an ultra-fast IC logic known as Rapid Single Flux Quantum (RSFQ) logic, with performance capable of enabling envisioned software radios     

High-speed frequency dividers with quasi-normally-off GaAs MESFETs

Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.     

射频锁相环型频率合成器的CMOS实现

本论文实现了一个射频锁相环型频率合成器,它集成了压控振荡器、双模预分频器、鉴频鉴相器、电荷泵、各种数字计数器、数字寄存器和控制电路以及与基带电路的串行接口.它的鉴频鉴相频率、输出频率和电荷泵的电流大小都可以通过串行接口进行控制,还实现了内部压控振荡器和外部压控振荡器选择、功耗控制等功能,这些都使得该频率合成器具有极大的适应性,可以应用于多种通信系统中.该锁相环型频率合成器已经采用0.25μm CMOS工艺实现,测试结果表明,该频率合成器使用内部压控振荡器时的锁定范围为1.82GHz~1.96GHz,在偏离中心频率25MHz处的相位噪声可以达到-119.25dBc/Hz.该频率合成器的模拟部分采用2.7V的电源电压,消耗的电流约为48mA.     

Design and analysis of a low-power discrete phase modulator in a 0.13-/spl mu/m logic CMOS process

This letter reports the design and analysis of a low-power discrete constant envelope phase modulator. The modulator discretely changes the phase of a constant envelope carrier according to the input digital data bits. A test chip was fabricated in a 0.13-/spl mu/m logic complementary metal oxide semiconductor process. The modulator consumes 2mA from a 1.2-V supply, has an operating frequency range between 1.5GHz and 3.3GHz, and can support a data rate up to 225Mbps with better than 5.5% error vector magnitude. The modulator can be designed to generate different modulation schemes by digitally controlling the phase and/or amplitude of the carrier, and therefore potentially can be used in software defined radios.     

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68 MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6 mW. The proposed design has been fabricated and verified in a 0.18 μm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4 bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213 GHz. The measured phase noise is −112.25 dBc/Hz at 1 MHz offset from the 1.819 GHz carrier and draws a current of 4.0 mA around at a 1.8 V supply.     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

A very wide bandwidth digital VCO using quadrature frequencymultiplication and division implemented in AlGaAs/GaAs HBT's

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm×1.6 mm and dissipates 2.45 W at a supply voltage of -6.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog     

Improving Radio Frequency Transmission Properties of Graphene via Carrier Concentration Control toward High Frequency Transmission Line Applications

Graphene has been gradually studied as a high‐frequency transmission line material owing to high carrier mobility with frequency independence up to a few THz. However, the graphene‐based transmission lines have poor conductivity due to their low carrier concentration. Here, it is observed that the radio frequency (RF) transmission performance could be severely hampered by the defect‐induced scattering, even though the carrier concentration is increased. As a possible solution, the deposition of the amorphous carbon on the graphene is studied in the high‐frequency region up to 110 GHz. The DC resistance is reduced by as much as 60%, and the RF transmission property is also enhanced by 3 dB. Also, the amorphous carbon covered graphene shows stable performance under a harsh environment. These results prove that the carrier concentration control is an effective and a facile method to improve the transmission performance of graphene. It opens up the possibilities of using graphene as interconnects in the ultrahigh‐frequency region.