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1.
由于硅器件尺寸不断缩小至纳米尺度,人们因此对纳米尺度器件开展了理论与结构方面的广泛而深入的研究,其中最重要的纳米尺度器件是基于碳纳米管的电场效应器件并被称为碳纳米管场效应晶体管(CNTFET).本文分析了碳纳米管场效应晶体管沟道电子的传输特性,并给出了用器件端子参数描述的器件I-V特性方程表达式,计算了器件的I-V特性曲线并把结果与纳米器件专用分析软件nanoMOS-2.0给出的结果作了比较,发现本文模型的计算结果均大于nanoMOS-2.0给出的结果,表明本文模型尚需进一步的深入分析和优化.  相似文献   

2.
综述了碳纳米管场效应晶体管(CNTFET)的主要结构和导电沟道的制备工艺,如AFM探针操控、CVD原位生长、交流介电泳和L-B大面积操控排布等方法。在对CNTFET的这些结构和制备工艺进行详细分析的基础上,着重指出目前CNTFET导电沟道制备中存在的诸如金属性单壁碳纳米管(SWCNT)的烧除、接触电阻大、滞后现象以及p型CNTFET转化等问题,并针对这些问题提出了具体可行的解决方案。  相似文献   

3.
Carbon nanotubes (CNTs) have been seen as a potentially future material to provide an ultrasmall device (CNTFET (Carbon Nanotube Field Effect Transistor)). Therefore, the studies of sub-bands effects are needed in order to find the enhancement of carrier transport in CNTFET.Also in this paper the band structure of the rolled-up nanotube can be obtained by zone-folding from the band structure of the graphene sheet. This method is used in this work and we simulated and analyzed the band structure of carbon nanotube. We present analytical modeling of carrier concentration in a zigzag semiconducting of carbon nanotube field effect transistor (CNFET) using the dispersion relation E(k) (the first three sub-bands) and given the density of states (DOS), the carrier concentration is obtained based on a numerical method as an alternative to the usual Fermi–Dirac integrals. In order to find the influence of the first three sub-bands energy and diameter dt of CNT in non-degenerate and degenerate region of the carrier concentration in CNTFET. The results obtained showed that the diameter and the energy of sub-band have a significant impact on the carrier concentration of CNTFET.  相似文献   

4.
Vertically aligned arrays of multi-walled carbon nanotubes were grown by pyrolysis of acetylene on iron catalytic particles within a porous silicon template via chemical vapor deposition (CVD) at 700 °C. Using this method ordered nanotubes with diameters from 75 to 100 nm could be produced. The diode configuration field emission of the CNT arrays were performed and the onset electric field is 4 V/μm and the emission current can approach 1 mA/cm2 at a electric field of 9.5 V/μm. The enhancement factor of the CNT arrays (4012) is derived from the F–N plot of the experiment data. To demonstrate the uniformity of the field emission, an ITO glass substrate with phosphor coated is used as anode in the field emission experiment. The average fluctuation of the emission current density was less than 5%. The result shows that the field emission of the CNT arrays on the silicon substrate is very uniform. These carbon nanotube arrays are useful for applications in field emission displays and sensors. The fabrication method shows the feasibility of integration between carbon nanotube arrays and silicon microelectronics.  相似文献   

5.
The selective growth of vertically aligned carbon nanotubes (CNTs) and their application as field‐effect transistors (FETs) are demonstrated. Vertically aligned carbon nanotubes were selectively grown in nanoholes formed in an anodized aluminum oxide (AAO) template. Each device element is formed on a vertical carbon nanotube attached to bottom (source) and upper (drain) electrodes and a gate electrode, which can be integrated in large arrays with the potential for tera‐level density (1012 cm–2). Simulation of the potential distribution shows that the direction of potential formation would depend on the polarity of the gate bias, which is consistent with an experimental result of CNT‐FET operation.  相似文献   

6.
In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.  相似文献   

7.
The origins of gate‐induced hysteresis in carbon nanotube field‐effect transistors are explained and techniques to eliminate this hysteresis with encapsulating layers of methylsiloxane and modified processes for nanotube growth are reported. A combined experimental and theoretical analysis of the dependence of hysteresis on the gate voltage sweep‐rate reveals the locations, types, and densities of defects that contribute to hysteresis. Devices with designs that eliminate these defects exhibit more than ten times reduction in hysteresis compared to conventional layouts. Demonstrations in individual transistors that use both networks and arrays of nanotubes, and in simple logic gates built with these devices, illustrate the utility of the proposed approaches.  相似文献   

8.
A method of patterning large arrays of organic single crystals is reported. Using single‐walled carbon nanotube (SWNT) bundles as patterned templates, several organic semiconductor materials were successfully patterned, including p‐type pentacene, tetracene, sexiphenylene, and sexithiophene, as well as n‐type tetracyanoquinodimethane (TCNQ). This study suggests that the selective growth of crystals onto patterned carbon nanotubes is most likely due to the coarse topography of the SWNT bundles. Moreover, we observed that the crystals nucleated from SWNT bundles and grew onto SWNT bundles in a conformal fashion. The dependence of the number of crystals on the quantity of SWNT bundles is also discussed. The crystal growth can be directly applied onto transistor source‐drain electrodes and arrays of organic single‐crystal field effect transistors are demonstrated. The results demonstrate the potential of utilizing carbon nanotubes as nucleation templates for patterning a broad range of organic materials for applications in optoelectronics.  相似文献   

9.
利用匀胶机将经过超声混合的二氧化硅小球的酒精溶液旋涂在洗净的硅片上,获得了具有曲面的纳米碳管生长基底.利用以二茂铁和二甲苯作为反应前驱体的化学气相沉积法在该基底上实现了碳管在二氧化硅与硅之间的选择性生长,并在不同的沉积温度条件下,可以分别获得球状和束状碳管产物.通过扫描电镜观察分析经过退火处理的原始基底的表面形貌,讨论了碳管产物与反应温度之间的关系.  相似文献   

10.
考虑到碳纳米管的几何形貌会在一定程度上影响其场发射性能,如驱动电场,发射电流强度等,因此本文设计了三种不同的几何图案,并采用热气相化学沉积(TCVD)法制备出了相应几何结构的定向碳纳米管阵列;通过模拟计算和场发射测试实验,我们对以上三种结构的场发射性能进行比较,发现具有规则六边形蜂窝形状的碳纳米管阵列具有最强的边缘效应,最小的屏蔽效应,以及相同电场下最大的发射电流。  相似文献   

11.
以多壁碳纳米管为基本材料,利用电子束诱导沉积的方法进行了纳米结构加工、修饰研究.电子束诱导沉积实现了二个碳纳米管端部之间的牢固焊接,实现了纳米材料间的几乎无损伤连接.原位测量表明多壁碳纳米管间的连接为欧姆接触.进一步对碳纳米管施加外电场可以使端部碳原子间的π键打开,外部碳原子经电子束诱导沉积在碳纳米管的端部,并定向生长成非晶态碳纳米线.由于碳纳米管和纳米线结合处的.键作为绝缘界面,形成了电子输运的势垒,所得到的碳纳米管-纳米线复合结构具有整流特性.利用电子显微镜进行纳米材料的结构加工、修饰,具有选择位置精确、可实时监测、对纳米材料几乎无损伤、重复性和可靠性高,以及加工尺度可人为控制的特点.  相似文献   

12.
Analog Integrated Circuits and Signal Processing - This paper presents carbon nanotube field effect transistor (CNTFET) implementation of voltage differencing current conveyor (VDCC). We propose...  相似文献   

13.
The effects of lightly doped drain and source (LDDS) and hetero-material-gate (HMG) structure on the static characteristics and switching speed performance for a carbon nanotube field effect transistor (CNTFET) have been theoretically investigated by a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green׳s functions (NEGF) solved self-consistently with Poisson׳s equation. A comparison study of electrical characteristics in conventional single-material-gate CNTFET (C-CNTFET), LDDS-CNTFET, HMG-CNTFET and LDDS-HMG-CNTFET structures has been performed. Simulations show that, compared with the other structures, LDDS-HMG-CNTFET significantly decreases leakage current, subthreshold swing, and increases on/off current ratio. In addition, effects of the gate electrode work function of the LDDS-HMG-CNTFET have been studied theoretically. The results indicate that the electron transport efficiency, and the cutoff frequency of the device, can be optimized by reasonably selecting the gate electrode work function. This work illustrates that the proposed LDDS-HMG-CNTFET might be useful for low-power high-speed CNTFET digital design.  相似文献   

14.
Nano‐objects would be of great interest for the development of new types of electronic circuits if one could combine their nanometer scale with original functionalities beyond the conventional transistor action. However, the associated circuit architectures will have to handle the increasing variability and defect rate intrinsic to the nanoscale. In this context, there is a very fast growing interest for memory devices, and in particular resistive memory devices, used as building blocks in reconfigurable circuits tolerant to defects and variability. It was recently shown that optically gated carbon nanotube field effect transistors (OG‐CNTFETs) based on large assemblies of nanotubes covered by an organic photoconductive thin film can be operated as programmable resistors and thus used as artificial synapses in circuits with function‐learning capabilities. Here, the potential of such approach is evaluated in terms of scalability by integrating and addressing several individually programmable resistances on a single carbon nanotube. In addition, the charge storage mechanism can be controlled at a length scale smaller than the device length allowing to also program the direction in which the current flows. It thus demonstrates that a single nanotube section can combine all‐in‐one the properties of an analog resistive memory and of a rectifying diode with tunable polarity.  相似文献   

15.
This paper presents a novel design of a high performance full adder cell based on carbon nanotube field-effect transistors (CNTFET). This full adder cell has been designed to be used in ripple carry adder (RCA) optimally so that carry-propagation delay decreases without increase in hardware costs. High speed in RCA structure, the low number of transistors and simplicity in design are the main advantages of the proposed design in comparison with the previous works. Moreover, to increase the proposed RCA speed, carry-propagation chain has been reduced to six cells using only 14 transistors per 4 bits in the worst case, regardless of the adder width. The simulation results using HSPICE demonstrate that a significant improvement in delay, power and power-delay product compared with the state-of-the-art works can be achieved. The results in different temperatures, supply voltages, frequencies and load capacitors have also been obtained.  相似文献   

16.
由于具有独特的一维纳米结构、稳定的化学特性和优异的电学性能,单壁碳纳米管被认为是制作高性能电子器件以及下一代纳米电路的理想材料,作为新型基础电子元件的一种,碳纳米管场效应晶体管一直是研究的热点。研究了一种基于非对称肖特基接触的碳纳米管场效应晶体管,金属钯与金属铝分别作为电极材料制作出的碳纳米管场效应晶体管分别表现出p型和n型的导通特性,当这两种金属分别作为源、漏电极制作在单根半导体性单壁碳纳米管的两端时,便构成了非对称肖特基接触结构碳纳米管场效应晶体管。器件表现出了优良的整流特性,整流比达到103,在栅压的调控下,正向电流的开关比接近103。  相似文献   

17.
The temperature dependence of the electrical characteristics of field‐effect transistors (FETs) based on polymer‐sorted, large‐diameter semiconducting carbon nanotube networks is investigated. The temperature dependences of both the carrier mobility and the source‐drain current in the range of 78 K to 293 K indicate thermally activated, but non‐Arrhenius, charge transport. The hysteresis in the transfer characteristics of FETs shows a simultaneous reduction with decreasing temperature. The hysteresis appears to stem from screening of charges that are transferred from the carbon nanotubes to traps at the surface of the gate dielectric. The temperature dependence of sheet resistance of the carbon nanotube networks, extracted from FET characteristics at constant carrier concentration, specifies fluctuation‐induced tunneling as the mechanism responsible for charge transport, with an activation energy that is dependent on film thickness. Our study indicates inter‐tube tunneling to be the bottleneck and implicates the role of the polymer coating in influencing charge transport in polymer‐sorted carbon nanotube networks.  相似文献   

18.
A self-limiting dielectrophoresis technique, aimed at deterministically assembling individual or bundles of single-walled carbon nanotubes (SWCNTs) and multiwalled carbon nanotubes (MWCNTs), is experimentally investigated. A limiting resistor is used to control the electric field after the deposition of a single carbon nanotube. The role of some key parameters such as voltage and duration of the deposition with and without the limiting resistor is studied.  相似文献   

19.
We demonstrate the use of microstructures as an inducement for the growth of patterned and aligned carbon nanotubes (CNTs) during thermal chemical vapor deposition process. The growth of individual nanotube lines of vertical-standing 8-10 μm length can be controlled in almost any directions. In directions of approximate 90°, 60°, 45° or 0° relative to substrate surface, kinds of aligned CNTs patterns were synthesized. We also show that the flow of carrier gas and apical dominance like plant growth are the main factors of patterning CNTs, which indicates that the distribution of electric field can be controlled and the shielding effects can be weakened. The result establishes a method of patterned and aligned nanotubes, which is well suited for ordered arrays of CNTs field emitters. The field emission currents were observed to be fairly reproducible ranging from 375 to 1000 V and field emission measurements show a low turn-on field (1.25 V/μm).  相似文献   

20.
A novel vacuum field emission differential amplifier integrated circuit (VFE diff-amp IC) utilising carbon nanotube (CNT) emitters is presented. A dual-mask microfabrication process is employed to achieve the VFE diff-amp IC by integrating identical CNT VFE transistors with built-in split gates and anodes. The pair of integrated amplifiers shows low gate turn-on voltage, large DC gain, a reasonable transconductance, and a good common-mode rejection ratio. The approach demonstrates a new way for development of temperature- and radiation-tolerant VFE integrated microelectronics.  相似文献   

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