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1.
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI 总被引:2,自引:0,他引:2
Po-Chiun Huang Yi-Huei Chen Chorng-Kuang Wang 《Solid-State Circuits, IEEE Journal of》2000,35(10):1474-1480
This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm2 using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW 相似文献
2.
A general gain-enhancement technique for operational amplifiers using a replica amplifier is described. Unlike conventional techniques such as cascoding, which increases the gain by increasing the output resistance, the replica-amp technique increase the gain by matching the main and the replica amps. Among the advantages of the replica-amp technique are low supply, high swing, and effectiveness with resistive loads. This technique has been demonstrated in a 1.2-μm CMOS two-stage op amp. Operating from ±1-V supplies, the op amp has an effective open-loop dc gain of greater than 10 000, while maintaining a high swing of 100 mV from either supply rails. The gain-enhancement circuit is shown to have only a small effect on the settling time experimentally, analytically, and in SPICE simulation 相似文献
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A 1.5-V, 1.5-GHz CMOS low noise amplifier 总被引:11,自引:0,他引:11
A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices 相似文献
5.
1V高线性度2.4GHz CMOS低噪声放大器 总被引:2,自引:0,他引:2
讨论了低噪声放大器(LNA)在低电压、低功耗条件下的噪声优化及线性度提高技术.使用Chartered 0.25μm RF CMOS 工艺设计一个低电压折叠式共源共栅LNA.后仿真结果表明在1V电源下,2.36GHz处的噪声系数NF仅有1.32dB,正向增益S21为14.27dB,反射参数S11、S12、S22分别为 -20.65dB、-30.27dB、-24dB,1dB压缩点为-13.0dBm,三阶交调点IIP3为-0.06dBm,消耗的电流为8.19mA. 相似文献
6.
A 0.6-V subthreshold-leakage suppressed fully differential CMOS switched-capacitor amplifier using Analog T-switch scheme in a standard 0.18 μm CMOS technology is presented. The circuit design of major building blocks is described. The performance of this circuit is demonstrated by experimental results. The experimental results confirm the capability of Analog T-switch scheme to fulfill circuit requirements. 相似文献
7.
A 0.9-V 0.5-μA, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode nMOS transistors buffer a bulk-driven pMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low-voltage translinear control circuit 相似文献
8.
Kuang-Hu Huang Wei-Cheng Wang Tang-Huei Yang Chorng-Kuang Wang 《Solid-State Circuits, IEEE Journal of》1999,34(10):1373-1381
This paper proposes an AM-suppression CMOS amplifier that incorporates a discrete-level automatic gain control (AGC) with a hysteresis hard limiter in order to reduce magnitude dependent jitter and speed up AM-suppression response. The gain control that is composed of a transition-based magnitude controller and a discrete-level current-mode variable gain amplifier (VGA) does not require coherent detection and external components. The prototype amplifier demonstrates a jitter of 7.2° from 1-Mb/s pulse-point modulated (PPM) data input with 20-dB dynamic range (40-400 mVpp), which is six times improvement over the conventional limiter alone approach. The amplifier with an active area of 0.64 mm2 is implemented in 0.8-μm single-poly double-metal digital CMOS technology. It consumes 18 mW from a single 2-V supply 相似文献
9.
Rebeschini M. van Bavel N.R. Rakers P. Greene R. Caldwell J. Haug J.R. 《Solid-State Circuits, IEEE Journal of》1990,25(2):431-440
The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S /N . The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process 相似文献
10.
Steyaert M.S.J. Janssens J. de Muer B. Borremans M. Itoh N. 《Solid-State Circuits, IEEE Journal of》2000,35(12):1895-1907
This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-μm CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-μm CMOS technology, without tuning or trimming 相似文献
11.
A fully differential bipolar track-and-hold amplifier (THA) employs an open-loop linearization technique compatible with low supply voltage. A feedthrough reduction method utilizes the junction capacitance of a replica switch to provide a close match to the junction capacitance of the main switch. The differential full-scale (FS) input range is 0.5 V. In the track mode, with fin=10 MHz, FS sinewave input, the measured total harmonic distortion (THD) is less than -72 dB. With fs=300 MS/s and fin=10-50 MHz, FS sinewave input, the measured THD is less than -65 dB. This THD measurement reflects the held values as well as the tracking components of the output waveform. With fs<10 MS/s and fin=10-50 MHz, FS sinewave input, the measured feedthrough is less than -60 dB. The hold capacitance is 2.5 pF and the differential droop rate is 16 mV/μs. The THA consumes 32 mW from a 2.7-V power supply and is fabricated in a 0.5-μm, 18-GHz BiCMOS process 相似文献
12.
Nakamura M. Imai Y. Sano E. Yamauchi Y. Nakajima O. 《Solid-State Circuits, IEEE Journal of》1992,27(10):1421-1427
The design and performance of an AlGaAs/GaAs HBT limiting amplifier are presented. It is revealed that the main cause of phase shift deviation in a limiting amplifier is the bias dependence of the input capacitance, which is the dominant nonlinear factor in a transistor. A circuit design featuring a differential configuration with an emitter peaking technique lowers phase deviation and widens the frequency band. The device achieves high-frequency operation of 15 GHz with a low phase shift deviation of 3° over a 15-dB input dynamic range 相似文献
13.
A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V. 相似文献
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A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers 总被引:1,自引:0,他引:1
A CMOS limiting amplifier with a bandwidth of 3 GHz, a gain of 32 dB, and a noise figure of 16 dB is described. The amplifier is fabricated in a standard 2.5-V 0.25-μm CMOS technology and consumes 53 mW. Inversely scaled amplifier stages and active inductors with a low voltage drop are used to achieve this performance. The amplifier is targeted for use in 2.5-Gb/s (OC-48) SONET systems 相似文献
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Chun-Huat Heng Gupta M. Sang-Hoon Lee Kang D. Bang-Sup Song 《Solid-State Circuits, IEEE Journal of》2005,40(12):2525-2535
Superheterodyne TV tuners have been implemented in discrete forms using tunable RF and SAW IF filters. Integrating TV tuners in CMOS technology without them is a challenging task to cope with technical issues such as harmonic mixing and image. The image rejection in low- or zero-IF systems has been limited to 30-40 dB by analog imperfections such as I/Q path gain and phase mismatches. A single-chip low-IF TV tuner solution is proposed so that the image can be suppressed digitally using an image cancellation technique based on a complex one-tap LMS signal decorrelation algorithm. Programmable digital filtering and video/sound demodulation make a multistandard TV tuner feasible in the 48-860 MHz VHF/UHF band. The chip has a maximum gain of 63 dB and an input automatic gain control (AGC) range from -15 to 25 dB with 0.85-dB steps. It achieves an image and IF rejection of 60 dB, a peak carrier-to-noise ratio (CNR) of 55 dB, and a peak sound signal-to-noise ratio (SNR) of 44 dB without frequency modulation (FM) de-emphasis. The prototype occupies 6/spl times/6 mm/sup 2/ in 0.25-/spl mu/m CMOS and consumes 1 W at 2.5 V. 相似文献
18.
Crippa C. Nicollini G. Mecchia A. Rizzo P. Confalonieri P. Pernici S. Nagari A. Viani E. Bietti I. Adduci F. Mariani S. Calloni A. Moioli M. Mandelli S. Dallavalle C. 《Solid-State Circuits, IEEE Journal of》1999,34(2):170-181
A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 μW, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70°C. Chip area (including scribe line) is 55.5 mm2 in a 0.8 μm N-well double-metal single-poly CMOS process with implanted capacitors 相似文献
19.
The design and measured performance of a two-stage third-order ΣΔ (sigma-delta) analog-to-digital (A/D) converter is described. The A/D converter achieves a 96-dB dynamic range and a maximum signal-to-noise-plus-distortion ratio (S /(N + D )) r.m.s./r.m.s. of 93 dB with 320-kHz output rate and an oversampling ratio of 64. An analysis of the integrator gain error is presented. The modulator is realized in a 1.2-μm double-metal single-poly CMOS process with an active area of 1.6 mm2. This modulator operates from a 5-V power supply and a single reference voltage 相似文献
20.
A modified switched-opamp technique is proposed to enable switched-capacitor (SC) circuits to operate at 1 V with the opamp fully functional in all phases. A 1-V fully differential two-switchable-output-pair operational amplifier has been designed for the proposed technique, which is then employed in a 1-V fully differential SC pseudo-2-path filter. Implemented in a standard single-poly triple-metal 0.5-μm CMOS process, the filter achieves a sixth-order bandpass response centered at 75 kHz with a quality factor of 45. Capacitors formed with polysilicon and highly doped n-well (cap-well option) regions are used to achieve both good linearity and small chip area. At 1-V supply, the filter obtains an output swing of 1.2 Vpp and a dynamic range of 51 db while dissipating 310 μW and occupying a chip area of 0.8 mm2 相似文献