短沟道双栅MOSFET二维表面势解析模型

采用分解电势的方法求解二维泊松方程,建立了考虑电子准费米势的短沟道双栅MOSFET的二维表面势模型,并在其基础上导出了阈值电压、短沟道致阈值电压下降效应和漏极感应势垒降低效应的解析模型。研究了不同沟道长度、栅压和漏压情况下的沟道表面势,分析了沟道长度和硅膜厚度对短沟道效应的影响。研究结果表明,电子准费米势对开启后的器件漏端附近表面势有显著影响,新模型可弥补现有模型中漏端附近表面势误差较大的缺点;对于短沟道双栅MOSFET,适当减小硅膜厚度可抑制短沟道效应。     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合.     

非对称异质双栅应变硅MOSFETs 二维模型研究

基于对二维泊松方程的精确求解,本文对全耗尽型非对称异质双栅应变硅MOSFET的二维表面势,表面电场,阈值电压进行了研究。模型结果和二维数值模拟器的结果很吻合。此外并对该器件的物理作了深入的研究。该模型对设计全耗尽型非对称异质双栅应变硅MOSFET器件有着重要的指导作用.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应，在沟道源端一侧引入了高掺杂Halo结构．通过求解二维电势Poisson方程，为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型，并对其性能改进情况进行了研究．结果表明，新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应，并进一步提高载流子输运效率．新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱，但随Halo区长度非单调变化．解析模型与数值模拟软件MEDICI所得结果高度吻合．     

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。     

非对称HALO结构的全耗尽SOI二维阈值电压解析模型

在考虑了隐埋层与硅层的二维效应的基础上提出非对称HALO结构的全耗尽SOI二维阈值电压解析模型,该模型计算了在不同硅膜厚度,掺杂浓度,HALO区占沟道比例的条件下的阈值电压.模型结果与二维数值模拟软件MEDICI的模拟结果较好的吻合,该模型对HALO结构的物理特性和工艺设计有很好的指导意义.     

全耗尽阶梯掺杂沟道围栅MOSFET二维解析模型

采用分离变量法求解柱坐标系下二维泊松方程,建立了考虑耗尽电荷和自由电荷的全耗尽阶梯掺杂沟道围栅MOSFET的二维体电势模型,并在此基础上得到阈值电压和亚阈值摆幅的解析模型。研究了不同区域长度和漏压下的表面势,分析了不同掺杂的区域长度和掺杂浓度对器件性能的影响。结果表明,与均匀掺杂的GAA MOSFET相比,阶梯掺杂结构不仅降低了漏端电场,而且能更好地抑制短沟道效应和热载流子效应;通过对掺杂区域参数进行优化,可以提高器件的可靠性。     

双栅MOSFET沟道侧壁绝缘柱(DP)表面势解析模型

采用抛物线近似方法求解二维泊松方程,建立了漏端沟道侧壁绝缘柱表面电势解析模型。在该解析模型下,求解了不同漏压下的表面势,并与Atlas仿真结果做对比。比较了在相同条件下,DPDG MOSFET与DG MOSFET的沟道侧壁电势与电场分布。在不同沟道长度下,分析了DPDG MOSFET器件的阈值电压(Vth),亚阈值斜率(SS)以及漏感应势垒降低效应(DIBL),并与DG MOSFET作对比。结果表明,添加绝缘柱DP后,不仅减小了源漏端电荷分享,而且增强了栅对电荷控制,从而改善了器件的DIBL效应,并有效提高了器件的可靠性。     

双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

Analytical modeling of InSb/AlInSb heterostructure dual gate high electron mobility transistors

This paper presents an approximate solution of a 2D Poisson’s equation within the channel region for Double-Gate AlInSb/InSb High Electron Mobility Transistors (DGHEMTs), using variable separation technique. The proposed model is used to obtain the surface potential, electric field, threshold voltage and drain current of both tied and separated gate bias conditions for Double-Gate AlInSb/InSb HEMTs. The surface potential and electric field are derived for both effective conduction paths of front and back heterointerface by a simple analytical expression and an analytical solution is verified with sentarus TCAD device simulator.     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed (as in the case of the DG MOSFET); instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential (eQFP) decreases as the channel potential starts to decrease, and there are hiphops in the channel eQFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I-V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.     

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates

The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS^TM by Silvaco Inc.     

Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs-InGaAs symmetric double-gate HEMT

This paper presents an approximate solution of a 2-D Poisson’s equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results.     

Simulation and two-dimensional analytical modeling of subthresholdslope in ultrathin-film SOI MOSFETs down to 0.1 μm gate length

The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 μm. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S -factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found     

Short channel MOSFET model using a universal channel depletionwidth parameter

We verified a critical rendition that short channel effects depend on junction depth, and showed that junction depth by itself is not important for improving short channel immunity. The depletion region width of a short channel device changes significantly depending on the location along the channel. We proposed a universal channel depletion width parameter that effectively expresses this dependence. Using this parameter, we solved a two-dimensional (2-D) potential distribution and derived a threshold voltage model. The model reproduces the numerical data of sub-0.1-μm gate length devices, including channel doping concentration, gate oxide thickness, drain voltage, and back bias dependencies     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.