PLL调频立体声接收机制作

锁相环(PLL)电路PLL(锁相环)电路的基本组成如图1。压控振荡器(VCO)是一种用电压控制振荡频率的电路。假定基准振荡器的频率为100kHz,若要构成一个700MHz 的PLL 路,VCO 的输出需经过分频系数 N=700的分频器。也得到一个100kHz 的信号,若两者完全相同,比较器输出的 VCO 的控制电压不变,就能得到稳定的70MHz 的输出。由于某种原因使频率发生变化,经比较器和 LPF 输出的电压产生高低变化,对 VCO 的振荡频率起到补偿作用,使振荡稳定。若频率增高,加在 VCO 上的电     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

FRS家用对讲机的原理、调试与维修(四)

3.PLL锁相环电路工作原理本对讲机系统的PLL锁相环电路采用日本东芝TB31202芯片,能使两个锁相环路同时工作。FRS-1对讲机实际上只用了其中的一个锁相环。R50、R51、R52、C74、C71、C72、R53、C73、R54组成了VCO误差电压输出的低通滤波器,将把此误差电压脉冲信号转变成相对应的直流电压信号,再通过L19电感滤波去控制VCO振荡的频率,使其与系统提供的基准频率保持一致。当VCO振荡频率大于系统的基准频率时,锁定检测     

一种用于Bluetooth发接器的倍频式VCO

介绍了一种适用于 Bluetooth发接器的 ,可以单片集成的倍频式压控振荡器 ( VCO)。这种 VCO由两部分组成 ,主 VCO的振荡频率是所需本振频率的一半 ,然后采用“注入锁频”原理对主 VCO的振荡频率进行倍频以产生本振信号。主 VCO和倍频电路都使用了片上集成螺旋电感 ,调谐用的变容元件使用 PMOS晶体管实现。经过版图设计和后仿真 ,在 TSMC0 .35 μm数字 COMS工艺 ,3.3V电源电压下 ,该 VCO在 2 .4GHz中心频率附近可以达到的相位噪声指标为 -1 2 5 d Bc/Hz( 60 0 k Hz) ,在输出摆幅为 60 0 m Vp- p时 ,功耗为 2 2 m W。     

1.9～5.7 GHz宽带低噪声BiCMOS LC VCO

设计了一种宽带、低相位噪声差分LC压控振荡器(VCO)。所设计的电路采用开关电容阵列和开关电感,实现了多波段振荡输出。对负阻环节跨导进行了优化设计,将热噪声控制在最小范围内,同时采用高品质因数片上螺旋电感,以减小电路的噪声干扰。采用台积电(TSMC)0.35μmSiGe BiCMOS工艺制作了流片,并进行了仿真和硬件电路实验。实测结果表明,当调谐电压为0～3.3 V时,可设定VCO工作在6个波段(1.9～2.1 GHz,2.1～2.4 GHz,2.4～3.0 GHz,3.0～3.4 GHz,3.4～4.2 GHz,4.2～5.7 GHz),此6波段连续可调,构成了1.9～5.7 GHz宽带VCO;VCO的中心频率为2.4 GHz、偏离中心频率为1 MHz时实测相位噪声为-111.64 dBc/Hz;在3.3 V电源电压下实测核静态电流约为1.8 mA,从而验证了宽带、低噪声BiCMOS LC VCO设计方案之正确性。     

利用锁相环的简单调频信号发生器

利用562型锁相环(PLL),以一个调幅信号调制其定时电路的电压,可以很快制作一个简单的调频信号发生器.这样组合成的调频振荡器具有频偏大而失真小的优点.电路中,电容C_(10)决定着锁相环内压控振荡器(VCO)的固有振荡频率.音频输入电压加到A点对这个频率进行调制,而后在端子4输出.图中的参数是为调频接收机的需要以10.7MC选定的.电阻R_(11)提功频率细调,可以在中心频率上调整±10%.压控振荡器固有频率fo的变化,△f是A点电压R_7和R_8的函数,这个频偏可由下式算出:     

单片UHF RFID阅读器中VCO及其预分频器设计

提出了一种应用于860～960 MHz UHF波段单片射频识别(RFID)阅读器的低相位噪声CMOS压控振荡器(VCO)及其预分频电路.VCO采用LC互补交叉耦合结构,利用对称滤波技术改善相位噪声性能,预分频电路采用注入锁定技术,用环形振荡结构获得了较宽的频率锁定范围.电路采用UMC 0.18 μm CMOS工艺实现,测试结果表明:VCO输出信号频率范围为1.283～2.557 GHz,预分频电路的频率锁定范围为66.35%,输出四相正交信号.芯片面积约为1 mm×1 mm,当PLL输出信号频率为895.5 MHz时,测得其相位噪声为-132.25 dBc/Hz@3 MHz,电源电压3.3 V时,电路消耗总电流为8 mA.     

数字可编程的VCO

图1的电路是一种窄频带的VCO(压控振荡器),它具有设定数字以决定中心频率的可编程功能,其中心频率比(高频/低频)大于2:1。若对VCO再二分频,就可获得多种的振荡频率。该VCO的工作频率可大于230MHz(采用ECL器件),所以该电路可为用户提供高速的选通和禁止功能。     

一种全差分双路延迟环形VCO的设计

采用SMIC 40 nm CMOS工艺,设计了一款采用双路延迟结构和新型延迟单元的高性能全差分环形压控振荡器。仿真结果表明,该VCO电路可实现高振荡频率和宽调谐电压,调节频率范围为5.5~8 GHz,控制电压调节范围为0~VDD。谐振频率为6.25 GHz时,消耗功耗为4.4 mW,相位噪声为-85 dBc@1 MHz。该VCO可应用于高速IO时钟恢复及频率发生器电路中。     

一种基于FPGA实现的真随机数发生器

本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。电路为纯数字形式,50MHz采样时钟采得的输出数据可以无需后处理,直接通过随机性测试,且未发现随机性与采样频率存在显著联系。     

基于变结构混沌的伪随机序列发生器

为产生随机性能良好的伪随机序列,提出了一个新的变结构混沌系统。该混沌系统在一个开关函数控制下其系统结构随时间随机地转换,所产生的混沌信号是两个不同的混沌信号的混合,具有良好的复杂性。基于该变结构混沌系统设计了一种伪随机序列发生器,采用NIST标准和STS-2．0b测试套件对其产生的伪随机序列进行了统计性能测试,测试结果表明该伪随机序列发生器具有良好的随机性,可应用于计算机、通信、信息加密等领域中。     

7.5 Gb/s monolithically integrated clock recovery circuit using PLLand 0.3-μm gate length quantum well HEMT's

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V     

Logistic chaotic sequence generator based on physical unclonable function

Logistic nonlinear chaotic system has many good characters such as initial value sensitivity and topological mixing in the some parameter condition,which is used to create the random sequence signal generator.Because of the attributions of randomness and uniqueness even under the exact,the same circuit layouts and manufacturing procedures,there is still an instinct unclonable difference in each integrated circuit.Therefore,a new sequence stream generator was proposed based on Logistic chaotic system and physical unclonable function designed by double output look-up-table (LUT).The output of the Logistic sequence generator was associated with a specific physical circuit.This kind of sequence generator could resist an attack such as the replication of the keys of the system.The system was designed and tested on the Xilinx FPGA board.The results show that the same architecture of the circuit and the same config file operated on the different FPGA developing board can generate the total different random chaotic sequence stream and improve the randomness of the stream.     

低电压CMOS压控振荡器设计

设计和分析了一种低电压CMOS压控振荡器,对设计的电路进行理论分析和模型建立,并使用仿真工具对电路进行验证和优化。设计中主要考虑相位噪声和调谐宽度等指标,通过采用电感电容滤波技术以及合理调整电路结构和元器件参数,使相位噪声和调谐宽度均达到了较高的性能指标。结果表明,在1.2 V工作电压下,设计的VCO的尾电流为3 mA,输出振荡频率为2.24~2.57 GHz,中心频率约为2.4 GHz,调谐范围达到13.7%。     

基于混沌激光的500Mb/s高速真随机数发生器

基于光反馈半导体激光器产生混沌激光作为熵源,设计制作了放大器、比较器及触发器等高频电子器件,实现对混沌激光的模数转换,产生一路随机数,与另一路不相关的随机数异或处理,无需后续数字处理,最快可实现500 Mb/s输出。产生的随机数序列通过了美国国家标准与技术研究院(NIST)的统计测试标准(SP800-22)。该随机数发生器码率可调,易集成,有利于产品化。     

Design of efficient CMOS ring oscillator-based random number generator

Although studies have investigated the effects of flicker noise on randomness, such effects demand further examination. Despite the random nature of flicker noise, a coloured distribution is observed in the power spectral density of flicker noise, indicating to a correlation in between adjacent samples. Studies have employed ring oscillators (ROs) that produce random numbers by sampling the digitised analogue signals of their outputs. This sampling procedure may change the spectral properties of flicker noise resulting from the folding effect of noise. Another topic of interest regarding sampled flicker noise is its random behaviour. To investigate the contribution of flicker noise, white noise, and their combination to randomness, we produce synthetic bit streams of these noise sources. From observations, we find that flicker noise contributes to the entropy of bit streams. Using the generated synthetic bit streams, we also explore the entropy dependence of a bit stream on the sampling period and analyse and compare the entropy levels of the outputs of ROs operating in strong and weak inversion. Results of the comparison demonstrate that only one RO operating in weak inversion may be sufficient to attain the required entropy level for qualifying the generated bit stream as random. The results of the analysis are also confirmed by measurements. In addition, the paper proposes an efficient design of a RO-based random number generator.     

Emitter-coupled pair chaotic generator circuit

An emitter-coupled pair chaotic generator is proposed with a control parameter that can be tuned for distinct chaotic behaviors. The proposed circuit is a compact, high-speed implementation of the chaotic map based on the hyperbolic tangent function. It is demonstrated that the circuit and map parameters are analytically related. As an application, we design a random number generator that passes all NIST statistical tests by applying a post-processing to the balanced bit sequence generated by a quantization of the circuit output.     

Digital quasi-random modulated SFAVM PWM in an AC-drive system

A main research topic in PWM-VSI inverter-driven electrical machines is to reduce the generated acoustic noise which often is dominated by a multiple of the switching frequency in the inverter. This paper proposes a modulation scheme for reducing the acoustic noise effect from an AC machine which can be implemented digitally for low and high performance systems. The scheme is based on a stator flux asynchronous vector modulation (SFAVM) imposed by a digital band limited PWM white noise generator for varying the switching frequency randomly. The white noise generator can be used for 8, 16 and 32 bit microcontrollers. The modulation strategy is tested in a 1 kVA high performance 16 bit microprocessor controlled AC drive system. Voltage-spectra on the line-to-line voltage and the acoustic noise spectra are presented and show that the new modulation strategy can decrease the noise effect. The stator-flux-polygon and the line current are measured and demonstrate the random modulation strategy. Finally, the total sound pressure level from the AC machine is investigated with fixed switching frequencies and with different randomly modulated frequency spans. It is concluded that a properly chosen fixed switching frequency has the lowest total sound pressure level. However, the random modulation strategy distributes the noise frequencies and the noise is more comfortable and less annoying     

A low power current-reuse LC-VCO with an adaptive body-biasing technique

This work presents a low-power low-phase noise current-reuse LC voltage controlled oscillator (VCO) with an adaptive body-biasing technique that enhances the reliability of the proposed circuit under process, voltage, and temperature (PVT) variations. Furthermore, the supply voltage and power consumption of the proposed VCO are reduced by the start-up oscillation condition that is provided by the adaptive body-biased circuit. This property is in fact very interesting from the power management perspective. The proposed VCO works at carrier frequency of 1.8 GHz and draws the power of only 306 µW from a 0.9 V supply. It achieves phase noise of −123.36 dBc/Hz at 1 MHz offset and provides a figure-of-merit (FoM) of −193.61 dBc/Hz. The post-layout simulation results of designed VCO in 0.18 µm standard CMOS technology confirm the effectiveness of the proposed circuit.