A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

硅片键合界面的应力研究

本文主要研究硅片直接键合界面结构与应力大小.当抛光硅片直接键合时,界面出现极薄的过渡区,并存在微小的晶向差,但不引起多余应力.当热生长了二氧化硅层的硅片相键合时,界面存在二氧化硅层,并引起张应力,其大小与硅二氧化硅系统应力大小相当.     

Sealing of adhesive bonded devices on wafer level

In this paper, we present a low temperature wafer-level encapsulation technique to hermetically seal adhesive bonded microsystem structures by cladding the adhesive with an additional diffusion barrier. Two wafers containing cavities for MEMS devices were bonded together using benzocyclobutene (BCB). The devices were sealed by a combined dicing and self-aligning etching technique and by finally coating the structures with evaporated gold or PECVD silicon nitride. The sealing layer was inspected visually by SEM and helium leak tests were carried out. Devices sealed with silicon nitride and with known damage of the sealing layer showed a helium leak rate of about 7–14 times higher than the background level. Devices of the same size without damage in the sealing layer had a leak rate of only 1.5 times higher than the background level. Experiments with evaporated gold as cladding layer revealed leaking cracks in the film even up to a gold thickness of 5 μm. The sealing technique with silicon nitride shows a significant improvement of the hermeticity properties of adhesive bonded cavities, making this bonding technique suitable for applications with certain demands on gas-tightness.     

Steady-state measurement of wafer bonding cracking resistance

A steady-state wedge-opening test has been developed in order to measure the fracture toughness of bonded silicon wafers. Comparison between non-steady-state and steady-state tests is performed. The importance of allowing the rotation of the testing stage is discussed and appears to be essential in order to have the wedge perfectly aligned with the sample. Significant influence of (1) surface treatment; (2) thermal annealing; and (3) crack velocity on the toughness is observed for Si/Si wafer bonding and related to the interface chemistry.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides

Plain or structured hydrophillic silicon wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the wafer pairing chosen. If one or both wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the wafer surfaces just prior to bonding are described.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.

     

Three-dimensional micro-channel fabrication in polydimethylsiloxane(PDMS) elastomer

This paper describes a fabrication technique for building three-dimensional (3-D) micro-channels in polydimethylsiloxane (PDMS) elastomer. The process allows for the stacking of many thin (less than 100-μm thick) patterned PDMS layers to realize complex 3-D channel paths. The master for each layer is formed on a silicon wafer using an epoxy-based photoresist (SU 8). PDMS is cast against the master producing molded layers containing channels and openings. To realize thin layers with openings, a sandwich molding configuration was developed that allows precise control of the PDMS thickness. The master wafer is clamped within a sandwich that includes flat aluminum plates, a flexible polyester film layer, a rigid Pyrex wafer, and a rubber sheet. A parametric study is performed on PDMS surface activation in a reactive-ion-etching system and the subsequent methanol treatment for bonding and aligning very thin individual components to a substrate. Low RF power and short treatment times are better than high RF power and long treatment times, respectively, for instant bonding. Layer-to-layer alignment of less then 15 μm is achieved with manual alignment techniques that utilize surface tension driven self-alignment methods. A coring procedure is used to realize off-chip fluidic connections via the bottom PDMS layer, allowing the top layer to remain smooth and flat for complete optical access     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.     

Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging

Low temperature fluxless solder for wafer bonding has received a lot of attention due to its great potential in hermetic MEMS packaging. Previous research activities mainly deploy solder alloy of eutectic composition to achieve low bonding temperature. We proposed new intermediate bonding layers (IBLs) of rich Ag composition in In–Ag materials systems. In this study, we investigated the intermetallic compounds (IMCs) at the bonding interface with respect to the bonding condition, post-bonding room temperature storage and post-bonding heat treatment. With this IBL, the IMCs of Ag₂In and Ag₉In₄ with high temperature resist to post-bonding process are derived under process condition of wafer bonding at 180 °C, 40 min and subsequent 120–130 °C annealing for 24 h. Low melting temperature IMC phase of AgIn₂ is formed in the interface after long term room temperature storage or 70 °C aging treatment. This low melting temperature IMC phase can be completely converted into high melting temperature IMCs of Ag₂In and Ag₉In₄ after 120 °C additional annealing. Based on our results, we can design the packaging process flow so as to get reliable hermetic packaged MEMS devices by using low temperature fluxless In–Ag wafer bonding.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.