Electromigration lifetimes and void growth at low cumulative failure probability

We have investigated electromigration (EM) lifetimes and void formation at cumulative failure probability of around 50 ppm. We carried out EM test in damascene Cu lines using sudden-death test structures. Cumulative failure probability of the test ranges from 50 ppm to 90%. To investigate the void nucleation and growth behaviour, Cu microstructures were investigated by using scanning transmission electron microscopy (S-TEM) and electron backscatter diffraction (EBSD) technique. EM lifetime shows strong correlation with the void nucleation site and the void volume. In addition, the worst case for EM lifetime is that wide angle grain boundary exists just under the via as a void nucleation site.     

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.     

Electromigration induced aluminum atom migration retarding by grain boundary structure stabilization and copper doping

In order to clarify the relationship between Al line reliability and film microstructure, most notably grain boundary structure, we have tested three kinds of highly textured Al lines, namely a single-crystal Al line, a quasi single-crystal Al line and a hyper-textured Al line. Consequently, it has been shown that these kinds of lines have excellent endurance against electromigration (EM), compared with conventional Al lines deposited on TiN/Ti and SiO₂. The improvement of Al line reliability is attributable to the following factors; firstly, homogeneous microstructure and high activation energy, 1.28 eV, of the single-crystal Al line (ω=0.18°); secondly, subgrain boundaries, consisting of dislocation arrays found in the quasi single-crystal Al line (ω=0.26°), have turned out to be no more effective mass transport paths because dislocation lines are perpendicular to the direction of electron wind; finally, the decrease of the (1 1 1) full width at half maximum (FWHM) value promotes the formation of subgrain boundaries and low-angle boundaries, which have small grain boundary diffusivity, as revealed by the detailed orientation analysis of individual grains in the hyper-textured line (FWHM=0.5°) formed by using an amorphous Ta–Al underlayer (Toyoda H, Kawanoue T, Hasunuma M, Kaneko H, Miyauchi M. Proc. 32nd Ann. Int. Reliab. Phys. Symp., IEEE, 1994;178). Moreover, the diffusivity reduction and the uniformity of atomic flux result in the suppression of void/hillock pair in the Al lines. It has been clarified that a FWHM value is a useful criterion of reliability for an interconnection. Also, the Cu doping effect against EM endurance by using Cu implantation of the single-crystal Al lines has been examined. It has been clarified that EM lifetime is lengthened by about one order of magnitude for the Cu concentration of 0.1 at% in spite of almost the same diffusion coefficients. Moreover, the incubation time for a void nucleation has been observed even in the case of a pure-Al line. Thus, in accordance with the stress evolution model, it is concluded that the mechanism of lifetime improvement by Cu doping is such that critical stress for EM void nucleation is increased by the Cu doping. These results have confirmed that control of texture and/or grain boundary structure so as to suppress EM induced metal atom migration is a promising approach for the development of Al lines and Cu lines capable of withstanding the higher current densities required in future ULSIs.     

Analysis of electromigration induced early failures in Cu interconnects for 45 nm node

Bi-directional current stressing was used for monitoring electromigration (EM) lifetime evolution in 45 nm node interconnects. Experimental results show that an initial bimodal distribution of lifetimes can be modified into a more robust mono-modal distribution. Since the bi-directional tests provide successive void nucleation and void healing phases, the Cu microstructure is thought to evolve once the formed void is filled thanks to EM induced matter displacement. FEM modeling is used to compare the predicted location of void nucleation for given microstructures at the cathode end: a multigrain structure is compared to a perfect bamboo microstructure. Experimental and modeling results let us assume that small grains (<linewidth or via diameter) at the cathode end present a risk of EM induced early fails. Indeed at this location void nucleates and grows nearby the via opening it shortly. On the contrary, the bamboo microstructure is thought to provide more robust lifetime because voids nucleate a few hundred nanometers in the line and grow down reaching the bottom diffusion barrier of the line. This latter case provides larger void size before circuit opening.     

Experimental study of electromigration at bamboo grain boundarieswith a new test structure using the single-crystal aluminuminterconnection

Electromigration (EM) voids in the bamboo structure interconnect were observed by a new test structure with single-crystal aluminum leads. The new test structure consists of a single grain connected to single-crystal aluminum leads formed by lateral-solid phase epitaxial growth (L-SPE). The grain was formed by suppressing L-SPE of the single-crystal aluminum leads. Since the void nucleation sites were confined to the grain boundaries, the voids were easily located and observed. In addition, the crystal orientation of single-crystal aluminum leads could be controlled by L-SPE, and so the analysis could be performed more accurately than using traditional test structures that have a series of grains with random crystal orientation. The accelerated EM test was carried out under ideal conditions similar to that of real devices, because the temperature gradients around the test site of the bamboo grain boundaries were negligible. In our preliminary experiment, a void was observed in the grain, located next to the positive voltage lead. This seems to be contradictory to general understandings, we think this is because of the grain boundary configuration difference and/or EM induced vacancy fluxes difference     

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.     

Electromigration Studies of Cu/Carbon Nanotube Composite Interconnects Using Blech Structure

The electromigration (EM) properties of pure Cu and Cu/carbon nanotube (CNT) composites were studied using the Blech test structure. Pure Cu and Cu/CNT composite segments were subjected to a current density of $hbox{1.2} times hbox{10}^{6} hbox{A/cm}^{2}$. The average void growth rate of Cu/CNT composite sample was measured to be around four times lower than that of the pure copper sample. The average critical current-density–length threshold products of the pure Cu and Cu/CNT composites were estimated to be 1800 and 5400 A/cm, respectively. The slower EM rate of the Cu/CNT composite stripes is attributed to the presence of CNT, which acts as trapping centers and causes a decrease in the diffusion of EM-induced migrating atoms.      

Influence of Bias-Enhanced Nucleation on Thermal Conductance Through Chemical Vapor Deposited Diamond Films

This work describes an experimental study of the cross-plane thermal conductance of plasma-enhanced chemical vapor deposited (PECVD) diamond films grown as a result of bias-enhanced nucleation (BEN). The diamond films are grown on silicon wafers using a two-step process in which a nucleation layer of amorphous or diamond like (DLC) carbon is first deposited on the silicon under the influence of a voltage bias. Then, conditions are adjusted to allow for polycrystalline diamond (PD) growth. The nucleation layer is essential for seeding diamond growth on smooth substrates and for optimizing PD properties such as grain size, orientation, transparency, adhesion, and roughness. A photoacoustic (PA) technique is employed to measure the thermal conductivities of and the thermal interface resistances between the layers in the diamond film structure. The influence of nucleation layers that are 70, 240, 400, and 650 nm thick on the thermal conductance of the diamond film structure is characterized. The thermal conductivity of the nucleation layer exhibits a thickness dependence for relatively thin layers. For each sample, the thermal conductivity of the PD is higher than 500 Wldrm^-1K^-1 (measurement sensitivity limit). A resistive network for the diamond film structure is developed. The resistance at the silicon/nucleation interface is less than 10^-9m²ldrKldrW^-1 (measurement sensitivity limit), which is of the order of theoretical predictions. The minimum diamond film structure resistance occurs when the nucleation layer is thinnest. When the nucleation layer is sufficiently thick, it begins to exhibit bulk behavior, and the resistance at the nucleation/PD interface dominates the thermal resistance of the diamond film structure.     

A compact model for early electromigration failures of copper dual-damascene interconnects

A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.     

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.     

Formation and control of defects during molecular beam epitaxial growth of HgCdTe

Void defects were demonstrated to form away from the substrate-epifilm interface during the molecular beam epitaxial growth of mercury cadmium telluride on cadmium zinc telluride substrates. These were smaller in size compared to voids which nucleated at the substrate-epifilm interface, which were also observed. Observations of void nucleation away from the substrate-epifilm interface were related to the respective growth regimes active at the time of the void nucleation. Once nucleated, voids replicated all the way to the surface even if the flux ratios were modified to prevent additional nucleation of voids. For a significant number of films, void defects were observed co-located with hillocks. These voids were usually smaller than 1 μm and appeared almost indistinguishable from unaccompanied simple voids. However, these void-hillock complexes displayed a nest of dislocation etch pits around these defects upon dislocation etching, whereas unaccompanied voids did not. The nests could extend as much as 25 μm from the individual void-hillock complex. The density of dislocations within the nest exceeded 5×10⁶ cm⁻², whereas the dislocation density outside of the nest could decrease to <2×10⁵ cm⁻². The void-hillock complexes formed due to fluctuations in growth parameters. Elimination of these fluctuations drastically decreased the concentrations of these defects.     

Recent advances on kinetic analysis of electromigration enhanced intermetallic growth and damage formation in Pb-free solder joints

A comprehensive kinetic analysis was established to investigate the electromigration (EM) enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints with Cu under bump metallization (UBM). The kinetic model takes into account Cu-Sn interdiffusion and current stressing. Derivation of the diffusion coefficients and the effective charge numbers for the intermetallic compounds is an essential but challenging task for the study of this multi-phase multi-component intermetallic system. A new approach was developed to simultaneously derive atomic diffusivities and effective charge numbers based on simulated annealing (SA) in conjunction with the kinetic model. A consistent set of parameters were obtained, which provided important insight into the diffusion behaviors driving the IMC growth. The parameters were used in a finite difference model to numerically solve the IMC growth problem and the result accurately correlated with the experiment. EM reliability test revealed that the ultimate failure of the solder joints was caused by extensive void formation and subsequent crack propagation at the intermetallic interface. This damage formation mechanism was analyzed by first considering vacancy transport under current stressing. This was followed by a finite element analysis on the crack driving force induced by void formation. This paper is concluded with a future perspective on applying the kinetic analysis and damage mechanism developed to investigate the structural reliability of the through-Si-via in 3D interconnects.     

Electromigration lifetime improvement of copper interconnect by cap/dielectric interface treatment and geometrical design

A significant improvement of electromigration (EM) lifetime is achieved by modification of the preclean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation prior to cap-layer deposition and adhesion of Cu/cap interface were found to be the critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration median-time-to-failure and activation energy. Effects of layout geometrical variation and stress current direction were also investigated.     

Influence of diffusion barriers on the nucleation and growth of CVD Cu for interconnect applications

Nucleation and growth behavior of Cu influence strongly the macroscopic properties of the resultant films. In this work the nucleation of CVD Cu on different underlayer materials is studied. It is found that nucleation on bare diffusion barrier surfaces leads to island growth and, therefore, bad wetting and adhesion. An enrichment of F, O and carbon was found at the interface between the CVD Cu film and the diffusion barrier. However CVD Cu deposited on top of Ta with a 200-Å PVD Cu layer on top results in good wetting. CVD Cu films grown on a PVD Cu layer expose a highly preferred 111 orientation. In this case SIMS analysis reveals a comparably low concentration of oxygen, carbon and flourine at the interface region between the CVD Cu and the barrier. These observations shed light on relevance of surface conditions for the CVD Cu deposition process. They significantly affect both film adhesion and crystal orientation, which are crucial for the use of CVD Cu as interconnect material.     

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.     

室温下Cu/Sn3.5Ag焊点/Cu体系中电迁移引发裂纹的形成

Electromigration （EM） behavior of Cu/Sn3.5Ag/Cu solder reaction couple was investigated with a high current density of 5 × 10^3 A/cm^2 at room temperature. One dimensional structure, copper wire/solder ball/copper wire SRC was designed and fabricated to dissipate the Joule heating induced by the current flow. In addition, thermomigration effect was excluded due to the symmetrical structure of the SRC. The experimental results indicated that micro-cracks initially appeared near the cathode interface between solder matrix and copper substrate after 474 h current stressing. With current stressing time increased, the cracks propagated and extended along the cathode interface. It should be noted that the continuous Cu6Sn5 intermetallic compounds （IMCs） layer both at the anode and at the cathode remained their sizes. Interestingly, tiny cracks appeared at the root of some long columntype Cu6Sn5 at the cathode interface due to the thermal stress.     

Electromigration-induced cracks in Cu/Sn3.5Ag/Cu solder reaction couple at room temperature

Electromigration (EM) behavior of Cu/Sn3.5Ag/Cu solder reaction couple was investigated with a high current density of 5× 103 A/cm2 at room temperature. One dimensional structure, copper wire/solder ball/copper wire SRC was designed and fabricated to dissipate the Joule heating induced by the current flow. In addition, thermomigration effect was excluded due to the symmetrical structure of the SRC. The experimental results in-dicated that micro-cracks initially appeared near the cathode interface between solder matrix and copper substrate after 474 h current stressing. With current stressing time increased, the cracks propagated and extended along the cathode interface. It should be noted that the continuous Cu6Sn5 intcrmetallic compounds (LMCs) layer both at the anode and at the cathode remained their sizes. Interestingly, tiny cracks appeared at the root of some long column-type Cu6Sn5 at the cathode interface due to the thermal stress.     

Process development and adhesion behavior of electroless copper on liquid crystal polymer (LCP) for electronic packaging application

Liquid crystal polymer (LCP) has potentially a very wide application as substrate material in electronic packaging applications because of its unique advantages. The work in this paper was performed to realize the metallization of LCP for the purpose of board fabrication, and to study the adhesion between deposited copper and LCP. A homogenous electroless plated copper layer on LCP with 4 to 5 /spl mu/m thickness was achieved, while it increased up to 40 /spl mu/m with the subsequent electroplating. The timescale of etching, deposit ion rate, and pH value were gradually changing during the plating process and the influences on copper layer quality were investigated. The adhesion force of the copper-LCP layer system was measured by a shear-off-method. Scanning electron microscopy (SEM) was used to check the surface morphology after etching and the interface after shearing on both the backside of the copper layer and the LCP side. The relationship between the shear-off adhesion of copper and the time of chemical etching before plating was examined, and the optimal etching time is discussed. Heat treatment after plating was used, and it was shown that this significantly improved the adhesion strength.     

Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, IEEE Int. Rel. Phys. Symp. Proc. (2002) 312-321; Y.K. Lim et al., Stress-induced voiding in multi-level copper/low-k interconnects, IEEE Int. Rel. Phys. Symp. Proc. (2004) 240-245]. Then, Cu/Ta interface properties at the bottom of via seem to be in the critical path for stress-voiding. In this paper, stress-voiding on 300 mm wafers in individual vias for different post electrochemical Cu deposition (ECD) anneals is studied. Electrical results show the clear benefit of hot plate and short furnace annealings. Microstructural characterizations indicate that impurities accumulation at Cu/Ta interface during long annealings could drive preferred void nucleation.