A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

一个开关电容电路的模拟和优化程序

本文介绍了一个以分析开关电容(SC)电路为目的面向用户的通用程序。该程序可以完成对SC电路的时域、频域和灵敏度模拟,可以对SC电路进行多目标优化,并可以求得SC电路的传输极点,且对电路的输入信号、开关序列、网络拓扑没有限制,文中提出了在改进节点法基础上求出电路传输极点的方法,以贡献的方式建立求传输函数对电容比的灵敏度方程,通过线性变换求得对电容比的灵敏度的方法和SC电路的多目标优化方法。最后给出了用该程序对SC电路进行模拟和优化的两个算例。     

SC电路混合分析的一种方法

本文提出了ＳＣ电路混合分析的一种方法，此法特别适合于计算机辅助电路分析，并且所推导的ＳＣ电路混合议程与状态议程有着紧密的联系，由此可方便地求得ＳＣ电路的频域传递函数。     

利用信号的循环平稳特性进行相干源的波达方向估计

本文提出一种修正的ＳＣ－ＳＳＦ方法,该方法适用于宽带和窄带源,不仅可解决循环相关源的问题,而且具有更好的噪声抑制特性,用蒙特卡下实该方法噪声抑制性能优于ＳＣ－ＳＳＦ〈并具有对相同循环频率的多个循环盯关源进行ＦＤＯＡ估计的能力。     

Comparison of diversity combining techniques for Rayleigh-fadingchannels

Several methods of diversity combining for a Rayleigh-faded channel are evaluated and compared. The methods considered are, for coherent reception, maximal ratio combining (MRC), selection combining (SC), and a generalization of SC, whereby the two (three) signals with the two (three) largest amplitudes are coherently combined. We will call this method second (third) order SC, and denote it SC2 (SC3). Similar techniques are also investigated for noncoherent reception, with equal gain combining (EGC) replacing MRC, and noncoherent versions of SC2 and SC3. Numerical results indicate that SC2 and SC3 significantly enhances the bit-error rate (BER) performance relative to that achievable with SC, and under certain conditions approaches the performance achieved by MRC or EGG. The performance enhancement of SC2 and SC3 is especially noticable for noncoherent reception, where EGC is seen to provide the best performance only for low BER values. In fact, when the BER is 10 ^-3 or greater, SC2 and SC3 performed comparably to EGG, and in some cases performed better than EGC     

Highly flat super-continuum generation from 2 ps pulses using 1 km-long erbium-doped fibre amplifier

A method for generating a supercontinuum (SC) that uses a long optical fibre amplifier is proposed. In this method, the distributed optical gain and the long interaction length enable one to generate the flat SC generation from picosecond pulses used in telecommunication systems. Flat SC generation over 34 nm from a 2 ps pulse train using a 1 km-long erbium-doped fibre is experimentally demonstrated.     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

对寄生电容不灵敏的开关电容有源滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭圆低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

开关电阻对SC放大器速度的影响和优化方法

在开关电容(SC)放大器中,由于MOS开关导通电阻的存在,会对其建立速度产生影响.首先使用跨导运算放大器的一阶线性模型推导了包含开关导通电阻的开关电容放大器的闭环传输函数,通过分析极点和零点的分布,研究了放大器中不同位置开关的导通电阻对阶跃响应的影响.进而提出了一种MOS开关的优化设计方法来缩短放大器阶跃响应的建立时间.最后使用电路仿真工具验证了该方法的有效性.     

减小SC滤波器中GB效应的新结构

本文讨论了在开关电容(SC)滤波器中如何减少增益带宽积(GB)效应的问题,提出了一个减少GB效应的新的双二次拓扑结构,此结构对寄生电容不敏感,并且具有很低的无源W0,Q灵敏度。以低通SC滤波器为例,给出了减小GB效应的具体设计方法。并用设计实例和实验结果证明了所得结论的正确性。     

NEW STRUCTURE OF SC FILTERS WITH REDUCED GB EFFECT

In this paper, the problem how to reduce the GB effect in SC filters is discussed. A new generalbiquadratic SC structure in which the GB effect is reduced is developed. The structure is stray-insensitiveand has very low W_0 and Q sensitivities. Using the low-pass SC filter for an example, method of reducingthe GB effect has been shown in detail.     

An Efficient and Accurate DC Analysis Technique for Switched-Capacitor Circuits

A simple but highly accurate method is proposed to find the dc parameters of active or passive switched-capacitor (SC) circuits. It is based on the dc model of a general SC branch.     

Spinal Cord Injury Detection and Monitoring Using Spectral Coherence

In this paper, spectral coherence (SC) is used to study the somatosensory evoked potential (SEP) signals in rodent model before and after spinal cord injury (SCI). The SC technique is complemented with the Basso, Beattie, and Bresnahan (BBB) behavior analysis method to help us assess the status of the motor recovery. SC can be used to follow the effects of SCI without any preinjury baseline information. In this study, adult female Fischer rats received contusion injury at T8 level with varying impact heights using the standard New York University impactor. The results show that the average SC between forelimb and hindlimb SEP signals before injury was relatively high ( ges0.7). Following injury, the SC between the forelimb and hindlimb SEP signals dropped to various levels (les0.7) corresponding to the severity of SCI. The SC analysis gave normalized quantifiable results for the evaluation of SCI and recovery thereafter using the forelimb signals as an effective control, without the need of any baseline data. This technique solves the problems associated with the commonly used time-domain analysis like the need of a trained neurophysiologist to interpret the data and the need for baseline data. We believe that both SC and BBB may provide a comprehensive and complementary picture of the health status of the spinal cord after injury. The presented method is applicable to SCIs not affecting the forelimb SEP signals.     

宽带匹配新算法——SC法

本文提出了一种新的宽带匹配网络设计算法——ＳＣ法，首次将级联网络的Ａ矩阵特性和递归等同技术结合起来，设计分布参数的宽带阻抗匹配网络。通过理论计算及实验证明了ＳＣ法能够大大改善天线的驻波比和增益性能，因此可以广泛应用于天线设计及微波领域中。     

Simple approach to analysis of switched-capacitor circuits with nonideal op-amps

A possible method for the simulation of nonideal op-amps with a finite gain and bandwidth by means of an equivalent SC circuit, containing ideal components, is presented. The approach is extended by the case of an op-amp with non-switched input SC building blocks.     

基于图像分块和优化累积能量图的线裁剪算法

针对传统线裁剪方法对图像过度裁剪造成失真的问题,该文提出一种基于图像分块的线裁剪方法。该方法把分块的思想融入到线裁剪并优化累积能量图,能在一定程度上保护图像主体区域,又兼顾背景区域的裁剪效果。分块是根据显著图的平均列累加能量向量按照逐列标记的方式把图像分成保护区域和非保护区域,再根据每个区域的面积来分配裁剪线的数目。在裁剪过程中,优化了累积能量图,降低了小面积显著主体被裁剪掉的可能性。在MSRA数据库上与目前流行的线裁剪及其改进的方法进行对比,并把各种方法得到的缩放结果图在互联网上进行主观评价测试,实验结果表明该文方法具有更好的主观缩放效果,对各类图像的缩放具有普适性。     

Modeling of capacitor impedance in switching converters

Switched capacitor (SC) converters are gaining acceptance as alternatives to traditional, inductor-based switching power converters. Proper design of SC converters requires an understanding of all loss sources and their impacts on circuit operation. In the present work, an equivalent resistance method is developed for analysis, and equivalent resistance formulae are presented for various modes of operation. Quasiresonant converters are explored and compared to standard SC converters. Comparisons to inductor-based switching power converters are made. A number of capacitor technologies are evaluated and compared for applications to both SC converters and inductor-based converters. The resulting model can be used to accurately predict and optimize converter performance in the design phase.     

对寄生电容不灵敏的开关电容有源FDNR滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭园函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭园低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters     

By-inspection analysis of switched-capacitor networks †

The recent advances in implementation of analogue MOS switched-capacitor (SC) networks have established a need for new methods of analysis of these circuits. In this paper an analysis method of SC networks operating with an n-phase clock is presented. The method is based on a building block approach which facilitates the derivation of a z-domain equivalent circuit. The equivalent circuit is then analysed using the flow-graph technique.