数字信号处理在雷达相噪测量中的应用

随着通信和雷达的发展,脉冲信号的相位噪声成了影响整个系统性能的重要因素之一,采用传统模拟相位检波法测量脉冲信号相位噪声是一个非常大的挑战,因为这样的测试系统非常复杂,并且在测量相位噪声之前需要非常繁琐的校准程序,先进的正交数字相位解调和幅度解调技术能很好地解决这个问题。采用正交数字相位解调和幅度解调技术的系统不需要相位检波器和复杂的校准程序,利用极低噪声的参考源和互相关技术,提高了系统动态范围和测量灵敏度,实现了一键式精密测量脉冲相位噪声和调幅噪声。     

Spur-reduced digital sinusoid synthesis

This paper presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering amplitude and phase values prior to wordlength reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output wordlength reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise can be made white, making the noise power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.     

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

一个新颖的用于CT0标准的数字收发器

介绍了一种新颖的用于CT0无绳电话标准的数字收发器.该收发器采用数字调制和解调技术来进行数据传输,取代了传统的模拟调制解调方式.在发射机中,使用小数分频锁相环实现了CPFSK调制;为了减小占用带宽,使用了2RC整形技术.在接收机中,使用了一种新颖的数字解调方法实现2RC CPFSK信号的解调.该芯片采用SMIC 0.35μm混合信号工艺实现,芯片尺寸为2mm×2mm.使用片外的低噪声放大器,该芯片的接收灵敏度可达-103dBm.     

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or ${B}^{ast}$-tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.      

System Parameters and Performance of High Speed Modems on Analog Radio

High speed modems are a means for implementing early 100 percent digital connectivity in the transition to total digital networks. The system parameters for high speed data transmission over FM and SSB microwave radio are calculated. It is shown that radio fading is not necessarily a controlling factor. Other impairments such as noise, level, and phase transients are experienced on long terrestrial circuits. The setup for field measurements and results are presented. Technical and economic network criteria are presented that led to the decision to deploy 1.544 Mbit/s modems on analog microwave radio.     

Digital extraction of quantization error and its applications to successful design of sigma-delta modulator

A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a ? 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a ? 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.     

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.     

Scanning electron microscope image enhancement using spread spectrum through dither signal imposition

Noise is a primary issue in obtaining an image in a scanning microscope. This noise needs to be minimized in order to have a clear image of the sample in case of a nanosize level measurement. In this work, we propose a method to improve the image quality by applying dither signal injection to the scanning signal. This method involves minimizing the noise that occurs in scan control circuits, which results in a blurry or distorted image. The collected secondary electrons are first multiplied through a photomultiplier tube and are then converted into digital form using an analog/digital (A/D) converter. We propose a solution for the noise from the scan control circuit that appears on the image by adopting the spread spectrum method.     

On the development of a multifunction millimeter-wave sensor for displacement sensing and low-velocity measurement

A new multifunction millimeter-wave sensor operating at 35.6 GHz has been developed and demonstrated for measurement of displacement and low velocity. The sensor was realized using microwave integrated circuits and monolithic microwave integrated circuits. Measured displacement results show unprecedented resolution of only 10 /spl mu/m, which is approximately equivalent to /spl lambda//sub 0//840 in terms of free-space wavelength /spl lambda//sub 0/, and maximum error of only 27 /spl mu/m. A polynomial curve-fitting method was also developed for correcting the error. Results indicate that multiple reflections dominate the displacement measurement error. The sensor was able to measure speed as low as 27.7 mm/s, corresponding to 6.6 Hz in Doppler frequency, with an estimated velocity resolution of 2.7 mm/s. A digital quadrature mixer (DQM) was configured as a phase-detecting processor, employing a quadrature sampling signal-processing technique, to overcome the nonlinear phase response problem of a conventional analog quadrature mixer. The DQM also enables low Doppler frequency to be measured with high resolution. The Doppler frequency was determined by applying linear regression on the phase sampled within only fractions of the period of the Doppler frequency. Short-term stability of the microwave signal source was also considered to predict its effect on measurement accuracy.     

A virtual clock enhancement method for DDS using an analog delayline

In this paper, we describe an analog delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method is the immediate application of the output signal of the phase accumulator for the generation of the desired frequency. To obtain the necessary spectral purity of the generated frequency, additional digital signal processing (DSP) based on a delay-locked loop (DLL) and noise shaping is applied. The consequences of nonlinear effects within the DL for the spectral performance of the DDS are explained     

Measurement of Loop Gain with the Digital Modulator

A loop gain measurement technique for switching regulators using a digital modulator is introduced. While the conventional technique injects and measures the analog signals, the proposed digital modulator injects a digital perturbation and measures the resultant duty cycle modulation. Since the duty cycle signal, derived from all feedback loops, provides the ultimate control of a switching regulator, the loop gain defined at the duty cycle modulator is unique. Employing the digital modulator, this loop gain can be measured even with a switching regulator employing the current injected control. Furthermore, this new technique overcomes false measurement problems found in the conventional technique when the feedback signal at the point where the loop gain is measured contains a pulsating nature.     

Reducing the PLL noise bandwidth by a digital split-loop

The advantages of the split-loop technique for analog phase-locked loops with a time delay are well known. In this paper, it will be shown that the digital counterpart of the split-loop offers an additional advantage, since the first oscillator can already convert the incoming signal down into the baseband. If this signal is used for the demodulation, the noise bandwidth of the loop is reduced significantly without changing the acquisition and tracking ranges. The resulting noise bandwidth is calculated and compared to a conventional digital high-gain second-order loop. Furthermore, the effect on the BER performance for DQPSK modulation is simulated     

Modified FIR filter with phase compensation technique tofeedforward active noise controller design

In this paper, a finite-impulse response (FIR) filter with phase compensation is proposed to design the digital controller for active noise cancellation in ducts. This method can overcome the influence of delay effects, which arise from the analog devices, and then help to improve the ability of noise reduction. Moreover, all the control algorithms are implemented in a fixed-point-type digital signal processor that produces an antinoise signal to cancel noise in the authors' experiments. Experiments are demonstrated in a polyvinyl chloride material circular duct. It is proved that, by using the FIR filter with phase compensation, the reduction of broadband noise is about 20 dB, and about 50 dB of narrowband noise. The system also provides the ability to cancel the noise with two harmonic components, like automobile noise     

On the combining of the amplitude and phase modulation in the same signal

A method of contemporary use of digital and analog modulation on the same bandwidth is described. The phase of the carrier of an AM signal is modulated by a digital one. The rate of the digital signal depends on the RF bandwidth of the analog signal. The proposed technique can increase the bandwidth efficiency of existent communication systems. Measurements and results of a full hardware implementation will show the applicability of the method.     

Low cost video scaler and gray scale integrator

A hybrid digital/analog device capable of making high-resolution linear and area measurements from a standard monochromatic video image is described. The device is capable of dynamic as well as static data acquisition when used in conjunction with standard NTSC video recording equipment. Digital output allows for computer interfacing. Linear dimensions are obtained by electronically superimposing two horizontal and two vertical scaling lines on a video monitor. Each linear dimension has an eight-bit resolution and is displayed on the front panel with seven segment LEDs. Eight-bit, digital-to-analog converters are also used to provide analog outputs. A measurement of the temporal deformation pattern of the accessory capsule surrounding a mechanoreceptor (Pacinian corpuscles) in response to vibratory displacements is demonstrated. Area measurements are obtained via a window comparator, a 6 MHz clock, and a 16-bit digital-to-analog converter. Data is only valid within the zone set by the scaling lines, allowing data regions to be isolated from noise, etc. The 16-bit digital signal measuring the area of interest is then converted for analog output. The measurement of the consensual pupillary reflex in response to full-field illumination (Ganzfeld) is given as an example     

Nearly Shot-Noise-Limited Performance of Dual-Channel Linear Optical Sampling for Ultrafast DPSK Signals

This paper describes a newly developed dual-channel linear optical sampling technique for observing ultrafast optical differential phase-shift keying (DPSK) signals. As the proposed measurement scheme offsets two parallel interferometers by a relative delay corresponding to 1-symbol length of the DPSK signal, the measured phase distribution reflects the signal quality which is determined by the phase difference between adjacent symbols. This technique, based on interferometric optical gating by local short-pulses, also offers ultrafast measurement at symbol rates of greater than 100 Gsymbol/s. Moreover, its detection sensitivity can reach the shot noise limit. The waveform degradation caused by the coherence of the light source and the pattern effect of the phase modulator is successfully observed in continuous waves and 10-Gsymbol/s nonreturn-to-zero DPSK signals, and the constellation measurement is demonstrated for a 160-Gsymbol/s return-to-zero DPSK signal. Measurement system noise is also discussed for characterizing the detection sensitivity, and the nearly shot-noise-limited performance is experimentally verified.