The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

硅片背面软损伤工艺技术研究

硅中的金属离子杂质会明显降低少子寿命,并进一步影响硅器件的性能。因此对硅片背面喷砂工艺进行了系统的研究。通过喷砂工艺,在硅片背面形成软损伤层,使硅片具有了吸杂能力,并从吸杂机理出发,解决了吸杂工艺带来的硅抛光片表面颗粒效应,并对硅抛光片的吸杂效果及表面颗粒度进行了表征,为具有吸杂性能的“开盒即用”硅抛光片的批量化生产提供了有力的技术保证。     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Radiation thermometry of silicon wafers in a diffusion furnace forfabrication of LSI

A radiation thermometry technique suitable for measuring the temperature of silicon wafers in a diffusion furnace has been developed. A principal feature of this technique is that it measures the temperature of wafers that are not in the line of sight of a conventional pyrometer. An optical guide, consisting of two quartz prisms, gives optical access to interior wafers in the load. A measuring wavelength of 0.9 μm is selected since a silicon wafer is opaque and its emissivity does not depend on temperature at this wavelength. The accuracy of the thermometry is examined by comparing the measured value of the pyrometer with that of a thermocouple. The two measured values agree within ±2°C in a steady state. When wafers are being inserted into or drawn out from the furnace, however, an error is caused by the veiling glare at the optical guide and the wafer     

Photothermal Activation of Shallow Dopants Implanted in Silicon

Dopant impurities were implanted at high dose and low energy (10¹⁵ cm⁻², 0.5–2.2 keV) into double-side polished 200 mm diameter silicon wafers and electrically activated to form p–n junctions by 10 s anneals at temperatures of 1,025, 1,050, and 1,075°C by optical heating with tungsten incandescent lamps. Activation was studied for P, As, B, and BF₂ species implanted on one wafer side and for P and BF₂ implanted on both sides of the wafer. Measurements included electrical sheet resistance (Rs) and oxide film thickness. A heavily boron-doped wafer, which is optically opaque, was used as a hot shield to prevent direct exposure to lamp radiation on the adjacent side of the test wafer. Two wafers with opposing orientations with respect to the shield wafer were annealed for comparison of exposure to, or shielding from, direct lamp illumination. Differences in sheet resistance for the two wafer orientations ranged from 4% to 60%. n-Type dopants implanted in p-type wafers yielded higher Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been reduced. p-Type dopants implanted in n-type wafers yielded lower Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been increased. Effective temperature differences larger than 5°C, which were observed for the P, B, and BF₂ implants, exceeded experimental uncertainty in temperature control.     

Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Temperature measurement in rapid thermal processing using theacoustic temperature sensor

Acoustic techniques are used to monitor the temperature of silicon wafers in rapid thermal processing environments from room temperature to 1000°C with ±5°C accuracy. Acoustic transducers are mounted at the bases of the quartz pins that support the silicon wafer during processing. An electrical pulse applied across the transducer generates an extensional mode acoustic wave which is guided by the quartz pins. The extensional mode is converted into Lamb waves (a guided plate mode) in the silicon wafer which acts as a plate waveguide. The Lamb wave propagates across the length of the silicon wafer and is converted back into an extensional mode at the other pin. The extensional mode acoustic wave is detected and the total time of flight is obtained. The time of flight of the extensional mode in the quartz pin is measured using pulse echo techniques and is subtracted from the total time of flight. Because the velocity of Lamb waves in the silicon wafer is systematically affected by temperature, the measurement of the time of flight of the Lamb wave provides the accurate temperature of the silicon wafer. The current implementation provides a ±5°C accuracy at 20 Hz data rate. Further improvements in electronics and acoustics should enable ±1°C measurements. The acoustic temperature sensor (ATS) has several advantages over conventional temperature measurement techniques. Unlike pyrometric measurements, ATS measurements are independent of emissivity of the silicon wafer and will operate down to room temperature. ATS also does not have the contact and contamination problems associated with thermocouples     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

A technique for characterizing surface recombination in silicon wafers based on thermal-emission measurements

A noncontact technique for the measurement of the surface-recombination rate in silicon wafers is suggested. A wafer under study is excited optically in the spectral region of intrinsic absorption, and the excitation-wavelength dependence of the power of the wafer thermal emission beyond the intrinsic-absorption edge is examined. The surface-recombination rate is determined from the ratio of intensities of the wafer thermal emission in the wavelength range 3–5 μm recorded under excitation with two laser diodes with wavelengths of 863 and 966 nm. Wafers subjected to different surface treatments were tested; at 230°C, rates on the order of 10⁴ cm/s were measured after mechanical polishing and 10³ cm/s after etching in CP-4A etchant. The applicability of the method is discussed, and the measurement error as a function of the wafer and light-source parameters is considered.     

Experimental application of a quadratic optimal iterative learning control method for control of wafer temperature uniformity in rapid thermal processing

A quadratic-optimal iterative learning control (ILC) method has been designed and implemented on an experimental rapid thermal processing system used for fabricating 8-in silicon wafers. The controller was designed to control the wafer temperatures at three separate locations by manipulating the power inputs to three groups of tungsten-halogen lamps. The controller design was done based on a time-varying linear state-space model, which was identified using experimental input-output data obtained at two different temperatures. When initialized with the input profiles produced by multiloop PI controllers, the ILC controller was seen to be capable of improving the control performance significantly with repeating runs. In a series of experiments with wafers on which thermocouples are glued, the ILC controller, over the course of ten runs, gradually steered the wafer temperatures very close to the respective reference trajectories despite significant disturbances and model errors.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system     

Modeling of three-dimensional effects on temperature uniformity inrapid thermal processing of eight inch wafers

A three-dimensional steady-state model of the industry-standard AG Associates 4108 Heatpulse Rapid Thermal Processing system has been developed for the study of thermal uniformity across 8 inch wafers. The model combines radiation energy transfer among all solid surfaces in the chamber with energy transfer among the chamber materials and to the process ambient. Surfaces included are those of the tungsten filaments of the lamps, the silicon wafer, the polysilicon annular thermal guard ring, the quartz process tube, and the gold reflectors which surround the lamps and process tube. These surfaces are divided into approximately 4800 individual surface elements for the radiation transfer allowing very accurate thermal analysis. The model has previously been shown to provide very good agreement with experiment for temperature distributions across an 8 inch wafer. The model is presently used to make quantitative examinations of asymmetric effects occurring in a RTP chamber which cannot be examined by 2-dimensional models. Situations examined include the effect of nonuniform lamp power distributions. Also examined is tilting of the wafer with respect to the flow tube and reflective chamber     

Detection of oxygen concentration in silicon wafers using a tunable diode laser

Control of the oxygen concentration in silicon wafers is important for the fabrication of high quality integrated circuits. Techniques for the fast detection of oxygen would be desirable for production line quality control. The oxygen concentration in silicon has traditionally been measured by a Fourier transform infrared spectrometer (FTIS). Due to the slow response time (1-10 min), it is not suitable for wafer screening. In this report, we describe a diode laser spectroscopy technique for the fast (10 ms) detection of oxygen in production line silicon wafers. The results are in good agreement with those measured by the Fourier transform technique.     

Electric Current Dependence of a Self-Cooling Device Consisting of Silicon Wafers Connected to a Power MOSFET

A self-cooling device has been developed by combining a commercial n-channel power metal–oxide–semiconductor field-effect transistor (MOSFET) and single-crystalline Sb-doped n-type or B-doped p-type silicon wafers in order to improve the heat removal or cooling quantitatively. The electric current dependence of the temperature distribution in the self-cooling device and the voltage between the source and drain electrodes have been measured to estimate the Peltier heat flux. We found that the average temperature is decreased for a power MOSFET in which an electric current of 50 A flows. In particular, the average temperature of the power MOSFET was decreased by 2.7°C with the n-type Si wafer and by 3.5°C with the p-type Si wafer, although an electric current of 40 A makes little difference. This certainly warrants further work with improved measurement conditions. Nonetheless, the results strongly indicate that such n-type or p-type silicon wafers are candidate materials for use in self-cooling devices.