Programmable Ferromagnet-Semiconductor Logic Devices

The scopes for creating new programmable logic magnetoelectronics-based elements were reviewed. The functions of programmable logic were shown to be realizable by the Hall elements, spin-gate and spin-tunneling magnetoresistance elements, and magnetic nanodots combined with relatively simple semiconductor circuits. By means of magnetic programming of the basic logic functions, they can be realized like programmable logic constructions using magnetic devices as nonvolatile programmable elements or like matrices of universal logic elements. Ability to save program information and input data and to convert in one cycle the set of logic configurations are the main advantages of the discussed magnetic and ferromagnet-semiconductor logic devices.     

一种带信号调理的24位A/D转换器AD7714的原理及应用

AD7714是美国Analog-Devices公司生产的高精度模数转换芯片。它采用∑-△转换技术实现高达24位的精度。片内还含有可编程增益放大器、可编程数字滤波器和寄存器,串行接口可进行3线操作,很适合于灵敏的基于微控制和DSP的系统。本文简明扼要的介绍了AD7714芯片的原理和应用。     

QUBIT4MATLAB V3.0: A program package for quantum information science and quantum optics for MATLAB

A program package for MATLAB is introduced that helps calculations in quantum information science and quantum optics. It has commands for the following operations: (i) Reordering the qudits of a quantum register, computing the reduced state of a quantum register. (ii) Defining important quantum states easily. (iii) Formatted input and output for quantum states and operators. (iv) Constructing operators acting on given qudits of a quantum register and constructing spin chain Hamiltonians. (v) Partial transposition, matrix realignment and other operations related to the detection of quantum entanglement. (vi) Generating random state vectors, random density matrices and random unitaries.

Program summary

Program title:QUBIT4MATLAB V3.0Catalogue identifier:AEAZ_v1_0Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEAZ_v1_0.htmlProgram obtainable from:CPC Program Library, Queen's University, Belfast, N. IrelandLicensing provisions:Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.htmlNo. of lines in distributed program, including test data, etc.:5683No. of bytes in distributed program, including test data, etc.: 37 061Distribution format:tar.gzProgramming language:MATLAB 6.5; runs also on OctaveComputer:Any which supports MATLAB 6.5Operating system:Any which supports MATLAB 6.5; e.g., Microsoft Windows XP, LinuxClassification:4.15Nature of problem: Subroutines helping calculations in quantum information science and quantum optics.Solution method: A program package, that is, a set of commands is provided for MATLAB. One can use these commands interactively or they can also be used within a program.Running time:10 seconds-1 minute     

Shoot‐through current reduction scheme for low power LTPS TFT programmable shift register

This paper proposes a programmable pulse width shift register where an output pulse width is adjusted only by changing a start pulse width without any additional signals and reconfiguration for the pre‐charging scheme of high resolution and high frame rate active‐matrix flat‐panel displays. In addition, the overall power consumption of a proposed circuitry is dramatically reduced by alleviating the shoot‐through current of an interval inverter, compared with the previous shift registers with the programmable or fixed output pulse width. The proposed shift register is verified by the simulation program with integrated circuit emphasis (SPICE) simulation at low temperature poly‐Si thin film transistor process for 50 stages. The proposed shift register lessens the power consumption by 34% and 54% for the output pulse widths of two and 10 line times, respectively, compared with those of the previous shift register structures.     

EMPIRE: Empirical power/area/timing models for register files

With the growth of the embedded devices consumer market, power efficient hardware is needed. Therefore power-aware architectural exploration is one of the most crucial design steps. For such an exploration procedure, it is important to accurately model the power consumption of all main components of the embedded system. Registers and register files are one of the highest power consumers of any programmable processor, but there is a lack of accurate and publicly available models. This paper provides such a power model for standard cell based register files for 130 and 90 nm technologies. The proposed model provides dynamic power, leakage power, area and timing information for register files in terms of key parameters like width, depth, activity, ports, and capacitive loading. It is shown that current models capture neither correct absolute nor relative trends present in register files. It is shown that some key, but often neglected parameters like switching activity, load have a larger influence in some particular sizes of the register files than others. Therefore, using the Empire model, accurate architectural exploration is possible.     

可编程S盒及反馈移位寄存器的设计方法

可编程S盒和可编程反馈移位寄存器是可编程密码芯片的两个重要的部件。文章给出了可编程S盒和可编程反馈移位寄存器的一种逻辑设计方法,按照该方法设计的S盒能够通过编程实现任意的布尔逻辑函数,按照该方法设计的反馈移位寄存器能够通过编程灵活地改变反馈抽头和反馈函数。     

An Energy-Efficient Processor Architecture for Embedded Systems

We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.     

Limitations on post-processing assisted quantum programming

A quantum multimeter is a programmable device that can implement measurements of different observables depending on the programming quantum state inserted into it. The advantage of this arrangement over a single-purpose device is in its versatility: one can realize various measurements simply by changing the programming state. The classical manipulation of measurement output data is known as post-processing. In this work we study the post-processing assisted quantum programming, which is a protocol where quantum programming and classical post-processing are combined. We provide examples showing that these two processes combined can be more efficient than either of them used separately. Furthermore, we derive an inequality relating the programming resources to their corresponding programmed observables, thereby enabling us to study the limitations on post-processing assisted quantum programming.     

Online model predictive control of industrial processes using low level control hardware: A pilot-scale distillation column case study

Throughout the years, the computing power of industrial controllers has steadily increased. Together with the development of efficient quadratic program (QP) solvers, this raises the question whether these devices can host an online model predictive controller (MPC). The applicability of online MPC is investigated using a programmable automation controller (PAC) and a programmable logic controller (PLC) for the control of an industrially relevant process, i.e., a pilot scale distillation column. It is demonstrated that both devices are capable of hosting MPC, however the limitations of the PLC are reached for the investigated set-up. Finally, guidelines and pitfalls for use in practice are highlighted.     

锅炉房远程监控系统

系统用可编程序控制器实现对燃气锅炉的自动控制和远程监控。锅炉供暖面积达6000多平米,锅炉重达2万多吨。文中研究的内容是远程锅炉监控系统中的本地系统,采用模拟量采集模块RM416对现场数据进行采集,然后将其转换输入至PLC,PLC与个人计算机相连,利用STEP7-MICRO/WIN32将编好的控制程序输入到PLC可编程序控制器中,实现了对燃气锅炉的远程监控。     

The future of nanocomputing

We are aware that the semiconductor industry had already entered the nanotechnology world. The working group proposed a hierarchy consisting of four levels: devices, architecture, state variables and data representation. We review on 3D heterogeneous integration, quantum cellular automata, defect-tolerant architecture, quantum computing, nano devices and other novel devices. This experience suggests some criteria we will need to apply to bring these early research efforts into the realm of high-volume manufacturing.     

基于FPGA的全彩显示屏设计

系统介绍了一种以FPGA可编程逻辑器件为设计平台的、采用大屏幕全彩LED显示屏进行全彩图像显示的扫描控制器实现方案。阐述了系统各模块的工作原理及调试情况,给出了三色LED显示系统的仿真结果。     

Register spilling via transformed interference equations for PAC DSP architecture

Digital signal processors (DSPs) with very long instruction word (VLIW) data‐path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multibank register architectures are being adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. This paper addresses the issues of reducing the spill code for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register‐file architecture provides the opportunity to spill‐out register values onto different register banks. We present a conceptual framework based on the universal and the proxy interference graphs to model the live ranges of registers for spilling codes to different register banks. Heuristic algorithms are then developed on the basis of this concept. By heuristically estimating the register pressure for each register file, we treat different register banks as optional spilling locations in addition to traditional spilling to memory. Experiments were performed on the parallel architecture core VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64‐based compiler. The experimental results show that our approach can improve the performances on average for DSPStone and MiBench benchmarks with spilling cases by 7.1% and 21.6%, respectively, compared with the one always handling spill code in memory. Copyright © 2013 John Wiley & Sons, Ltd.     

Scalable architecture for quantum information processing with atoms in optical micro-structures

We review recent experimental progress towards quantum information processing and quantum simulation using neutral atoms in two-dimensional (2D) arrays of optical microtraps as 2D registers of qubits. We describe a scalable quantum information architecture based on micro-fabricated optical elements, simultaneously targeting the important issues of single-site addressability and scalability. This approach provides flexible and integrable configurations for quantum state storage, manipulation, and retrieval. We present recent experimental results on the initialization and coherent one-qubit rotation of up to 100 individually addressable qubits, the coherent transport of atomic quantum states in a scalable quantum shift register, and discuss the feasibility of two-qubit gates in 2D microtrap arrays.     

Impact of Reverse Computing on Information Locality in Register Allocation for High Performance Computing

Reversible computing aims at keeping all information on input and intermediate values available at any step of the computation, making information virtually present everywhere. Rematerialization in register allocation amounts to recomputing values instead of spilling them in memory when registers run out. In this paper we detail a heuristic algorithm for exploiting reverse computing for register materialization. This improves information locality as it provides more opportunities for retrieving data. Rematerialization adds instructions and we show on one specifically designed example that reverse computing may alleviate the impact of these additional instructions on performance. We also show how thread parallelism may be optimized on GPUs by performing register allocation with reverse recomputing that increases the number of threads per Streaming Multiprocessor. This is done on the main kernel of Lattice Quantum Chromo Dynamics simulation program where we gain a 11 % speedup.     

Computer-aided chemistry—II. A spectral database management program for use with microcomputers

A novel, specialized database management program, Spectra Manager, which organizes, manipulates, and plots spectral data, is described. The program, which was developed as a precursor to a database management program that will be used when all the spectral data recorded in a laboratory are stored on a common archival device, was designed specifically to handle 2-dimensional data sets completely graphically on the IBM S9000 laboratory computer. The IBM S9000 computer, which is based on the Motorola 68000 microprocessor, was selected because (i) high level languages can readily address memory in excess of 1 M byte, (ii) the processor is fast, and (iii) the IBM S9000 has a high resolution, memory-mapped CRT. These features allow the program to provide the scientist with a data processing environment that treats large sets of individual spectra much like numbers are tabulated and manipulated, with simple, spreadsheet-like database management programs. The program, also offers the scientist the novel capability of rapidly scanning through multiple sets of spectral data. Program and data manipulation functions are interactively controlled through on-screen menus and software programmable keys. Run-time monitoring information is displayed in four distinct display windows. Spectral data are input using standard or user-defined formats, and then manipulated with typical spectral processing procedures including: baseline subtraction, digital filter smoothing using a fast Fourier transform, and compilation of spectral overlay plots. The processed data can be output to devices such as a printer, plotter, or disk file. The program monitors each session and stores in a disk file, or prints on a printer, a summary of program activity that can be used as an audit trail.     

Local variable access behavior of a hardware-translation based Java virtual machine

Hardware bytecode translation is a technique to improve the performance of the Java virtual machine (JVM), especially on the portable devices for which the overhead of dynamic compilation is significant. However, since the translation is done on a single bytecode basis, a naive implementation of the JVM generates frequent memory accesses for local variables which can be not only a performance bottleneck but also an obstacle for instruction folding. A solution to this problem is to add a small register file to the data path of the microprocessor which is dedicated for storing local variables. However, the effectiveness of such a local variable register file depends on the size and the local variable access behavior of the applications.In this paper, we analyze the local variable access behavior of various Java applications. In particular, we will investigate the fraction of local variable accesses that are covered by the register file of a varying size, which determines the chip area overhead and the operation speed. We also evaluate the effectiveness of the sliding register window for parameter passing in context of JVM and on-the-fly optimization of local variable to register file mapping.With two types of exceptions, a 16-entry register file achieves coverages of up to 98%. The first type of exception is represented by the SAXON XSLT processor for which the effect of cold miss is significant. Adding the sliding window feature to the register file for parameter passing turns 6.2-13.3% of total accesses from miss to hit to the register file for the SAXON with XSLTMark. The second type of exception is represented by the FFT, which accesses more than 16 local variables for most of method invocations. In this case, on-the-fly profiling is effective. The hit ratio of a 16-entry register file for the FFT is increased from 44% to 83% by an array of 8-bit counters.     

Ergodic Quantum Computing

We propose a (theoretical) model for quantum computation where the result can be read out from the time average of the Hamiltonian dynamics of a 2-dimensional crystal on a cylinder.The Hamiltonian is a spatially local interaction among Wigner–Seitz cells containing six qubits. The quantum circuit that is simulated is specified by the initialization of program qubits. As in Margolus Hamiltonian cellular automaton (implementing classical circuits), a propagating wave in a clock register controls asynchronously the application of the gates. However, in our approach all required initializations are basis states. After a while the synchronizing wave is essentially spread around the whole crystal. The circuit is designed such that the result is available with probability about 1/4 despite of the completely undefined computation step. This model reduces quantum computing to preparing basis states for some qubits, waiting, and measuring in the computational basis. Even though it may be unlikely to find our specific Hamiltonian in real solids, it is possible that also more natural interactions allow ergodic quantum computing.PACS:03.67.Lx     

面向软错误的寄存器活跃区间分析

继性能和功耗问题之后,软错误导致的计算可信性已成为一个日益严峻的课题.由于寄存器访问频繁却未能被良好保护,发生在其中的软错误成为影响系统可靠性的关键因素之一.基于程序汇编代码,提出一种针对寄存器软错误的程序可靠性静态分析方法.首先通过数据流分析技术提取出可能影响程序执行的寄存器活跃区间,然后基于构成活跃区间的基本块集合计算其有效体系结构易感位数,在此基础上可定量计算寄存器软错误影响下的程序可靠性.基于MiBench基准程序的实验表明,该方法的分析结果与AVF分析法保持一致,同时还指出了寄存器相关活跃区间的关键程度,这为实现针对寄存器软错误的高效容错方法提供了依据.