The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

Silicon Resonator Based 3.2 $mu$W Real Time Clock With $pm$10 ppm Frequency Accuracy

This paper presents an ultra-low power generic compensation scheme that is used to implement a real time clock based on an AlN-driven 1 MHz uncompensated silicon resonator achieving 3.2 ?W power dissipation at 1 V and ±10 ppm frequency accuracy over a 0-50°C temperature range. It relies on the combination of fractional division and frequency interpolation for coarse and fine tuning respectively. By proper calibration and application of temperature dependent corrections, any frequency below that of the uncompensated resonator can be generated yielding programmability, resonator fabrication tolerances and temperature drift compensation without requiring a PLL. To minimize the IC area, a dual oscillator temperature measurement concept based on a ring oscillator/resistor thermal sensor was implemented yielding a resolution of 0.04°C. The IC was fabricated on a 0.18 ?m 1P6M CMOS technology.     

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

Ring Oscillator Technique for MOSFET $CV$ Characterization

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the $CV$ characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At $≪$1 MHz, the frequency divided output is compatible with standard in-line test. Data from experimental partially depleted silicon-on-insulator hardware at the 65-nm CMOS technology node are presented.      

Subthreshold Parallel FM-to-Digital $Delta$– $Sigma$ Converter With Output-Bit-Stream Addition by Interleaving

Single and parallel subthreshold frequency-modulation-to-digital $Delta$–$Sigma$ modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional parallel FDSM, reduces power, area, and complexity at the cost of using clocks with higher speed in its output stage. In addition, compared to the single FDSM, the parallel converter shows an improvement in signal-to-quantization-noise ratio of more than 25 dB at supply voltages as low as 300 mV.      

A Fully Differential Comparator-Based Switched-Capacitor $DeltaSigma$ Modulator

In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma $(DeltaSigma)$ modulator is presented. To ensure differential operation, the CBSC $DeltaSigma$ modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard 0.18-$muhbox{m}$ CMOS process. The active area is 0.21 $hbox{mm}^{2}$, and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s $(hbox{OSR} = 64)$.      

10-GHz 11.5-ps Pulse Generation From a Single-Mode Gain-Switched InGaAs VCSEL at 1.1 $mu$m

We have successfully generated a 10-GHz 11.5-ps pulse train at 1.1 $mu{hbox {m}}$ by using a gain switching technique with a high-speed and single-mode vertical-cavity surface-emitting laser (VCSEL). The InGaAs-based VCSEL we used had a sidemode suppression ratio of more than 50 dB and a modulation bandwidth of 7.2 GHz. A nearly transform-limited Gaussian pulse was obtained after chirp compensation, and the repetition rate can be increased up to 16 GHz. We also demonstrated a 10-Gb/s return-to-zero data modulation for the generated 10-GHz pulse train.      

A 5.6 GHz Low Power Balanced VCO in 0.18 $mu$m CMOS

A 5.6 GHz balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 mum CMOS 1P6M process. It consists of two single-ended complementary Colpitts LC-tank VCOs coupled by two pairs of varactors. At the supply voltage of 1.2 V, the output phase noise of the VCO is -119.13 dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.6 GHz, and the figure of merit is -190.29 dBc/Hz. Total VCO core power consumption is 2.4 mW. Tuning range is about 600 MHz, from 5.36 to 5.96 GHz, while the control voltage was tuned from 0 to 1.2 V.     

Extended Continuous Tuning of a Single-Frequency Diode-Pumped Vertical-External-Cavity Surface-Emitting Laser at 2.3 $mu$m

We report on single-frequency operation and wide mode-hop-free tuning range of a diode laser-pumped vertical- external-cavity surface-emitting semiconductor laser producing up to 3 mW around 2.3 $mu$m. An optically stable external cavity of only 1.4 mm is formed using a concave dielectric mirror of 2-mm radius. The maximum continuous tuning is about 500 GHz wide, obtained by a synchronized ramp of external cavity length and of the gain medium temperature. We used this tunable source to record a direct absorption spectrum of methane, which is found to match well a simulated spectrum from the HITRAN (high-resolution transmission molecular absorption database http://www.cfa.harvard.edu/hitran) database.      

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

Broadband Lumped-Element Integrated $N$-Way Power Dividers for Voltage Standards

This paper presents a monolithically integrated broadband lumped-element Wilkinson power divider centered at 20 GHz, which was designed and fabricated to uniformly distribute power to arrays of Josephson junctions (JJs) for superconducting voltage standards. This solution achieves a fourfold decrease in chip area, and a twofold increase in bandwidth (BW) when compared to the previous narrowband distributed circuit. A single Wilkinson divider demonstrates 0.4-dB maximum insertion loss (IL), a 10-dB match BW of 10–24.5 GHz, and a 10-dB isolation BW of 13–30 GHz. A 16-way four-level binary Wilkinson power divider network is characterized in a divider/attenuator/combiner back-to-back measurement configuration with a 10-dB match BW of 10–25 GHz. In the 15–22-GHz band of interest, the maximum IL for the 16-way divider network is 0.5 dB, with an average of 0.2 dB. The amplitude balance of the divider at 15, 19, and 22 GHz is measured to be ${pm}{hbox{1.0 dB}}$ utilizing 16 arrays of 15 600 JJs as on-chip power detectors.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

A K-Band High-Gain Down-Conversion Mixer in 0.18 $mu$m CMOS Technology

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.     

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.      

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

A Geometric Process $delta$-Shock Maintenance Model

A geometric process $delta$ -shock maintenance model for a repairable system is introduced. If there exists no shock, the successive operating time of the system after repair will form a geometric process. Assume that the shocks will arrive according to a Poisson process. When the interarrival time of two successive shocks is smaller than a specified threshold, the system fails, and the latter shock is called a deadly shock. The successive threshold values are monotone geometric. The system will fail at the end of its operating time, or the arrival of a deadly shock, whichever occurs first. The consecutive repair time after failure will constitute a geometric process. A replacement policy $N$ is adopted by which the system will be replaced by a new, identical one at the time following the $N$th failure. Then, for the deteriorating system, and the improving system, an optimal policy $N^{ast}$ for minimizing the long-run average cost per unit time is determined analytically.      

Modal Gain of 2.4- $mu$m InGaAsSb–AlGaAsSb Complex-Coupled Distributed-Feedback Lasers

High-resolution spectroscopy was used to examine gain characteristics of Cr-grating complex-coupled distributed-feedback (DFB) lasers near 2.4 $mu$m. The single-mode lasers contain InGaAsSb–AlGaAsSb active regions grown by molecular beam epitaxy on GaSb. Modal gain was extracted from the measured amplified spontaneous emission spectra and compared with reference Fabry–PÉrot lasers. The material gain is similar in both cases, having a value near 1300 cm$^{-1}$, while the internal losses are quite different. The DFBs have an additional loss, approximately equal to the lateral Cr grating coupling coefficient. This indicates a fundamental performance limitation for complex-coupled DFBs.      

Design of Exactly Linear Phase $K$-Regular IIR Half-Band Filter

This paper proposes a novel method to design exactly linear phase infinite impulse response half-band filters with arbitrary regularity. Broadly speaking, the design problem is formulated as a semi-infinite program, which is then turned into a semidefinite program of minimal order via a new linear matrix inequality characterization of convex hulls of trigonometric polynomials. In contrast to maximally flat approach, the proposed method allows direct control of various design parameters, which in turn enables the synthesis of filters with better transition response. The viability of the proposed method is demonstrated through several numerical examples.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

Optimization of Passively Repetitively $Q$-Switched Three-Level Lasers

A generalized model of a passively repetitively $Q$-switched three-level laser is presented. The method for evaluation of the small-signal gain coefficient and the dissipative losses of a three-level laser is shown. To demonstrate the use of this optimization procedure, it was applied to a microchip laser generating 1.5- $mu$m radiation. The model may be expanded for a four-level laser by replacing the calculation of the small-signal gain coefficient.