一种改进型MLSCR-ESD结构设计分析

集成电路中半导体器件的特征尺寸不断减小,集成电路对ESD的冲击更加敏感。静电防护成为集成电路中最重要的可靠性指标之一,ESD保护结构也成为芯片设计中的难题。随着集成电路规模的增大,芯片引脚增多,大量面积被用于ESD保护电路,导致成本提高。可控硅结构的ESD保护器件相比其他已知保护结构具有最高的单位面积ESD性能,因此成为低成本片上ESD设计方案的首选。针对改进型横向SCR (MLSCR,又称N+桥式SCR)的ESD保护结构,对其关键特性指标结合理论分析与实验数据进行分析。基于某0.18μm 5 V CMOS工艺的流片结果,对SCR结构的工作原理以及关键的触发电压、保持电压参数进行说明,并提出改进方案。     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

亚微米集成电路的ESD保护设计

介绍了一种带ESD瞬态检测的VDD-VSS之间的电压箝位结构,归纳了在设计全芯片ESD保护结构时需要注意的关键点;提出了一种亚微米集成电路全芯片ESD保护的设计方案,从实例中验证了亚微米集成电路的全芯片ESD保护设计.     

CMOS SoC芯片ESD保护设计

本文提出从器件失效功率的角度,解释CMOS SoC（System On Chip）芯片的ESD（ElectrostaticDischarge）失效原因,总结了CMOS集成电路（IC）的多种ESD失效模式,研究了多电源系SoC芯片的ESD保护设计方法,提出了SoC芯片的ESD保护设计流程。     

用于高压ESD防护的高维持电流SCR器件

静电释放(ESD)是指电荷在两个电势不等的物体之间转移的物理现象,它存在于人们日常工作生活的任意环节。随着集成电路特征尺寸不断减小、集成度不断增高,芯片对ESD也变得越来越敏感。为了用尽可能小的版图面积来实现ESD防护,利用晶闸管结构(SCR)来实现集成电路的ESD防护已成为当下的研究热点。但传统SCR的维持电压和维持电流都很低,若直接将其应用于电源ESD防护则会导致严重的闩锁效应(latch-up)。基于高维持电流设计窗口,提出一种可用于15 V电路的抗闩锁SCR器件,并通过混合仿真验证了该器件的有效性。     

基于CMOS工艺的全芯片ESD保护电路设计

介绍了几种常用ESD保护器件的特点和工作原理,通过分析各种ESD放电情况,对如何选择ESD保护器件,以及如何设计静电泄放通路进行了深入研究,提出了全芯片ESD保护电路设计方案,并在XFAB 0.6 μm CMOS工艺上设计了测试芯片.测试结果表明,芯片的ESD失效电压达到5 kV.     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

多电源混合电压SoC的全芯片ESD设计实例

SoC是含有微处理器、外围电路等的超大规模集成电路,具有器件特征尺寸小、复杂度高、面积大、数模混合等特点,SoC的ESD设计成为设计师面临的一个新的设计挑战。文章详细介绍了一个复杂的多电源、混合电压专用SoC芯片的全芯片ESD设计方案,并结合电路特点仔细分析了SoC芯片ESD设计的难点,提出了先工艺、再器件、再电路三个层次的分析思路,并将芯片ESD总体解决方案中的关键设计重点进行了逐一分析,最后给出了全芯片ESD防护架构的示意图。该SoC芯片基于0.35μm 2P4M Polycide混合信号CMOS工艺流片,采用文中提出的全芯片ESD防护架构,使该芯片的HBM ESD等级达到了4kV。     

一种新型的高维持电压可控硅

可控硅(SCR)作为静电放电(ESD)保护器件,因具有高的鲁棒性而被广泛应用,但其维持电压很低,容易导致闩锁问题。针对高压集成电路的ESD保护,提出了一种新颖的具有高维持电压的SCR结构(HHVSCR)。通过添加一个重掺杂的N型掺杂层(NIL),减小了SCR器件自身固有的正反馈效应,从而提高了SCR的维持电压。Sentaurus TCAD仿真结果表明,与传统的SCR相比,改进的HHVSCR无需增加额外的面积就可将维持电压从1.88 V提高到11.9 V,可应用于高压集成电路的ESD防护。     

基于SCR的双向ESD保护器件研究

可控硅整流器件(SCR)结构用于集成电路的静电放电(ESD)保护具有提高保护效率,减小芯片面积和降低寄生参数的优点.对基于SCR的双向ESD保护器件进行了研究;建立了一种ESD保护器件仿真设计平台,对该器件的结构、关键参数和性能进行了系统的仿真和优化.得到的改进器件不仅对ESD人体模型(HBM)的保护性能好,引入电路的寄生效应小,而且ESD保护的各关键性能参数也可以方便地进行调整.     

2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

SCR-based ESD protection in nanometer SOI technologies

This paper introduces an SCR-based ESD protection design for silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are sometimes better known, have long since been used in Bulk CMOS to provide very area efficient, high performance ESD protection for a wide variety of circuit applications. The special physical properties and design of an SOI technology however, renders straightforward implementation of an SCR in such technologies impossible. This paper discusses these difficulties and presents an approach to construct efficient SCR devices in SOI. These devices outperform MOS-based ESD protection devices by about four times, attaining roughly the same performance as diodes. Experimental data from two 65 nm and one 130 nm SOI technologies is presented to support this.     

Using an SCR as ESD protection without latch-up danger

A properly designed Low-Voltage Triggering SCR has a four times better ESD performance than a conventional grounded-gate NMOST of the same width. But it does present a latch-up risk due to its low holding voltage. The holding voltage can be increased by using a larger anode-to-cathode spacing, but at very large spacings the ESD performance decreases. It is shown that a window in SCR anode-to-cathode spacing exists, for which the holding voltage is sufficiently large, while the excellent ESD protection properties are preserved.     

A new multi-finger SCR-based structure for efficient on-chip ESD protection

This paper introduces a new SCR-based (silicon controlled rectifier) structure for on-chip ESD protection. The STMSCR (smart triggered multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR) using an external triggering circuitry that permits switching from a transparency mode to a protection mode as soon as an ESD event is detected. The trigger voltage can be adjusted by design without any impact on the ESD performance. The STMSCR is multi-finger compliant, thus allowing area-efficient design of pad-located ESD protection. The STMSCR is demonstrated in a 0.18 μm CMOS technology without any process customization; an HBM failure threshold over 115 V/μm is reached while always ensuring current uniformity in multi-finger structures.     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robustness under the positive-to-V_SS (PS-mode) ESD test, which is the most critical ESD-test pin combination. With a silicon-controlled rectifier (SCR) between the I/O pad and V_SS, the clamping voltage along the PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.