Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.     

Lasing at 1.28 /spl mu/m of InAs-GaAs quantum dots with AlGaAs cladding layer grown by metal-organic chemical vapor deposition

We report the device characteristics of stacked InAs-GaAs quantum dot (QD) lasers cladded by an Al/sub 0.4/Ga/sub 0.6/As layer grown at low temperature by metal-organic chemical vapor deposition. In the growth of quantum dot lasers, an emission wavelength shifts toward a shorter value due to the effect of postgrowth annealing on quantum dots. This blueshift can be suppressed when the annealing temperature is below 570/spl deg/C. We achieved 1.28-/spl mu/m continuous-wave lasing at room temperature of five layers stacked InAs-GaAs quantum dots embedded in an In/sub 0.13/Ga/sub 0.87/As strain-reducing layer whose p-cladding layer was grown at 560/spl deg/C. From the experiments and calculations of the gain spectra of fabricated quantum dot lasers, the observed lasing originates from the first excited state of stacked InAs quantum dots. We also discuss the device characteristics of fabricated quantum dot lasers at various growth temperatures of the p-cladding layer.     

Er-doped AlGaAs native oxides: photoluminescence characterization and process optimization

We present 300 K photoluminescence (PL) characterization data for wet thermal native oxides of Al/sub 0.58/Ga/sub 0.42/As films grown by metal organic chemical vapor deposition and doped with Er via multiple high-energy ion implants (for 0.0675, 0.135, and 0.27 atomic percent (at.%) peak Er concentrations), and Al/sub 0.5/Ga/sub 0.5/As and Al/sub 0.8/In/sub 0.2/As films doped with Er (0.03-0.26 at.%) during molecular beam epitaxy crystal growth. Broad spectra with a /spl sim/50-nm full-width at half-maximum and a PL peak at 1.534 /spl mu/m are observed, characteristic of Al/sub 2/O/sub 3/:Er films. The dependencies of PL intensity, spectra, and lifetime on annealing temperature (675/spl deg/C-900/spl deg/C), time (2-60 min) and As overpressure (0-0.82 atm) are studied to optimize the annealing process, with As considered as a possible quenching mechanism. Wet and dry-oxidized films are compared to explore the role of hydroxyl (OH) groups identified by Fourier transform infrared (FTIR) spectroscopy. FTIR experiments employing heavy water (D/sub 2/O) suggest that OH groups in wet oxidized AlGaAs come mainly from post-oxidation adsorption of atmospheric moisture. AlGaAs:Er films wet oxidized with 0.1% O/sub 2/ added to the N/sub 2/ carrier gas show a fourfold PL intensity increase, doubled PL lifetime to /spl tau//spl sim/5.0 ms (0.27 at.% implanted sample), and the lowest degree of concentration quenching.     

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.     

Magnetic resonance studies of trapping centers in high-/spl kappa/ dielectric films on silicon

The electrical properties of high dielectric constant materials being considered for replacements of SiO/sub 2/ in metal-oxide semiconductor (MOS) field effect transistors are dominated by point defects. These point defects play important roles in determining the response of these films in almost any imaginable reliability problem. A fundamental understanding of these defects may help to alleviate the problems which they can cause. The best known methods for determining the structure of electrically active defects in MOS materials and devices are conventional electron spin resonance (ESR) and electrically detected magnetic resonance (EDMR). In this paper, we review the limited ESR and EDMR work performed to date on high-/spl kappa/ materials. A discussion of magnetic resonance techniques as well as a brief overview of the extensively studied Si/SiO/sub 2/ system is also included.     

Stress-induced electromigration backflow effect in copper interconnects

The electromigration threshold in copper interconnect is reported in this paper. The critical product (jL)/sub c/ is first determined for copper oxide interconnects with temperature ranging from 250/spl deg/C to 350/spl deg/C from package-level experiments. It is shown that the product does not significantly change in this temperature range. Then, (jL)/sub c/ was extracted for copper low-k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than that for oxide dielectric was found. Finally, a correlation between the n values from Black's model and with jL conditions was established for both dielectrics.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

Dielectric relaxation in piezo-, pyro- and ferroelectric polyamide 11

Ferroelectric polyamide 11 films were prepared by melt-quenching, cold-drawing and electrical poling. Their ferroelectricity was studied by means of dielectric-hysteresis measurements. A remnant polarisation of up to 35 mC/m/sup 2/ and a coercive field of 75 MV/m were obtained. The piezoelectric d/sub 33/ coefficient and the pyroelectric coefficient of the films are reduced by annealing just below the melting region, but remain at about 3 pC/N and 8 /spl mu/C/(m/sup 2/K), respectively, during further heat treatment. Differential scanning calorimetry (DSC), dielectric relaxation spectroscopy (DRS) and thermally stimulated depolarisation (TSD) were applied for investigating the conformational changes induced by melt-quenching, cold-drawing and annealing. The results indicate that the cold-drawn film mainly consists of a rigid amorphous phase which exhibits considerably lower conductivity, no glass transition and consequently no dielectric /spl alpha/ relaxation. Instead, an /spl alpha//sub r/ relaxation is found, which is related to chain motions in regions of the rigid amorphous phase where the amide-group dipoles are not perfectly ordered. Annealing removes imperfectly ordered structures, but does not affect the ferroelectric polarisation. Therefore, it may be concluded that essentially the /spl alpha//sub r/ relaxation causes the thermally nonstable part of the piezo- and pyroelectricity in polyamide 11.     

Thermal resistance characterization of implanted subcollector InP-based HBTs

We present the results of measurements of thermal resistivity of the heterojunction bipolar transistor (HBT) devices, utilizing selective ion implantation to define the subcollector. This new device fabrication technique resulted in high-speed HBT devices with substantially reduced thermal resistivity, compared to devices utilizing the conventional fabrication approach which includes mesa isolation for pattern definition. The measurements were taken on full-thickness 3" InP wafers at T/sub amb/ from 30/spl deg/C to 180/spl deg/C and two separate emitter current densities. We present data on three device epitaxial structures with identical device layouts and discuss the relationship of V/sub be/ to temperature at these elevated power and temperature levels.     

Correlation between dielectric properties and sintering temperatures of polycrystalline CaCu/sub 3/Ti/sub 4/O/sub 12/

Dielectric properties of polycrystalline CaCu/sub 3/Ti/sub 4/O/sub 12/ (CCTO) pellets sintered in the temperature range 1000-1200/spl deg/C were evaluated with impedance spectroscopy at frequency range of 10/sup 2/ to 10/sup 7/ Hz from 90 K to 294 K. A correlation has been established between the pair values of low frequency limit dielectric constant and the total resistivity and the sintering temperature. For example, the sample sintered at 1100/spl deg/C demonstrates higher value of low frequency limit dielectric constant and lower value of total resistivity, while the sample sintered at 1000/spl deg/C demonstrates lower values of low frequency limit dielectric constant and higher value of total resistivity. This correlation has been successfully explained by relating with the difference in grain size and grain volume resistivities of these two polycrystalline CCTO samples. Further, it is suggested that donor doping of oxygen vacancies Vo' and Vo" may be the reason to cause the difference in the grain volume resistivities of these two samples.     

A 5-V operated MEMS variable optical attenuator by SOI bulk micromachining

We report the design, fabrication, and successful demonstration of microelectromechanical variable optical attenuator (VOA) using an electrostatic microtorsion mirror (0.6 mm in diameter) combined with a fiber-optic collimator. The VOA operates at low voltages (dc 5 V or less) for large optical attenuation (40 dB, corresponding to mirror angle of 0.3/spl deg/) and a fast response time (5 ms or faster). The mirror made of a bulk-micromachined silicon-on-insulator wafer has been designed to be shock resistant up to 500 G without any mechanical failure. We also have suppressed temperature dependence of optical performance to be less than /spl plusmn/0.5 dB at 10-dB attenuation in the range of -5/spl deg/C-70/spl deg/C by mechanically decoupling the parasitic bimorph effect from the electrostatic operation.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

Rated overload Characteristics of IGBTs for low-voltage and high-voltage devices

By a vertical shrink of the nonpunchthrough insulated gate bipolar transistor (NPT IGBT) to a structure with a thin n-base and a low-doped field stop layer a new IGBT can be realized with drastically reduced overall losses. In particular, the combination of the field stop concept with the trench transistor cell results in an almost ideal carrier concentration for a device with minimum on-state voltage and lowest switching losses. This concept has been developed for IGBTs and diodes from 600 V up to 6.5 kV. While the tradeoff behavior (on-state voltage V/sub CEsat/ or V/sub F/ to tail charge) and the overall ruggedness (short circuit, positive temperature coefficient in V/sub CEsat/, temperature independence in tail charge, etc.) is independent of voltage and current ratings the switching characteristics of the lower voltage parts (blocking voltage V/sub Br/<2 kV) is different in handling to the high-voltage transistors (V/sub Br/>2kV). With the HE-EMCON diode and the new field stop NPT IGBT up to 1700 V there is almost no limitation in the switching behavior, however, there are some considerations-a certain value in the external gate resistor has to be taken. High-voltage parts usually have lower current density compared to low-voltage transistors so that the "dynamic" electrical field strength is more critical in high-voltage diodes and IGBTs.     

Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO/sub x/N/sub y/ (EOT=20 /spl Aring/) gate dielectric under a two- stage constant voltage stress in inversion mode are physically analyzed with the aid of transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltage below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.     

Thermal-stability improvement of a sulfur-passivated InGaP/InGaAs/GaAs HFET

The temperature-dependent characteristics of an InGaP/InGaAs/GaAs heterostructure field-effect transistor (HFET), using the (NH/sub 4/)/sub 2/S/sub x/ solution to form the InGaP surface passivation, are studied and demonstrated. The sulfur-passivated device shows significantly improved dc and RF performances over a wide temperature range (300-510 K). With a 1/spl times/100-/spl mu/m/sup 2/ gate-dimension HFET by (NH/sub 4/)/sub 2/S/sub x/ treatment, the considerably improved thermal stability over dc performances including lower temperature variation coefficients on the turn-on voltage (-1.23 mV/K), the gate-drain breakdown voltage (-0.05 mV/K), the gate leakage current (1.04 /spl mu/A/mm/spl middot/K), the threshold voltage (-1.139 mV/K), and the drain-saturation-current operating regimes (-3.11/spl times/10/sup -4//K) are obtained as the temperature is increased from 300 to 510 K. In addition, for RF characteristics, the sulfur-passivated device also shows a low degradation rate on drain-saturation-current operating regimes (-3.29/spl times/10/sup -4//K) as the temperature is increased from 300 to 400 K. These advantages provide the promise for high-speed high-frequency high-temperature electronics applications.     

Characterization of Si implants in p-type GaN

Si ion implantation into p-type GaN followed by rapid thermal annealing (RTA) in N/sub 2/ has been performed. X-ray diffraction analyses indicate that ion-implanted damage remains even with 1050/spl deg/C, 60 s RTA. By varying implantation and postimplantation annealing conditions, we could convert carrier concentration from p-type 3 /spl times/ 10/sup 17/ cm/sup -3/ into n-type 2 /spl times/ 10/sup 17/ cm/sup -3/ /spl sim/2 /spl times/ 10/sup 19/ cm/sup -3/. It was found that typical activation energies of Si implants in p-GaN are lower than 10 meV. Such activation energies are smaller than those observed from epitaxially grown Si-doped GaN films. A deep donor level with activation energy of 60 meV was also found from some samples. Photoluminescence studies show that the peak appears at 372 nm might be related to implantation-induced defects. It was also found that a green emission band could be observed from Si-implanted GaN. It was shown that such a green emission is related to the yellow band observed from epitaxially grown Si-doped GaN. The transport properties of these Si-implanted samples were also studied.     

Analysis and modeling of LC oscillator reliability

In this paper, MOS device degradations due to hot carrier and gate oxide breakdown are shown experimentally, and their effects on the NMOS LC oscillator have been evaluated analytically and through SpectreRF simulation. The reduction in transconductance of the differential pair transistors may cause the oscillation to cease. The amplitude of oscillation reduces as the equivalent tank resistance decreases due to the breakdown effect on the MOS varactor. The reduction of amplitude reduces the tank capacitances, and therefore shifts the frequency of oscillation and increases the oscillator phase noise. The tank amplitude of the oscillator is derived analytically. A closed-form expression for the average capacitance of the varactor that accounts for large-signal effects is presented. Finally, a set of guidelines to design an LC oscillator in reliability is presented.     

The impact of LOC structures on 670-nm (Al)GaInP high-power lasers

We investigate the potential of large optical cavity (LOC)-laser structures for AlGaInP high-power lasers. For that we study large series of broad area lasers with varying waveguide widths to obtain statistically relevant data. We study in detail I/sub th/, /spl alpha//sub i/, /spl eta//sub i/, and P/sub max/, and analyze above-threshold behavior including temperature stability and leakage current. We got as expected for LOC structures minimal /spl alpha//sub i//spl les/1 cm/sup -1/ resulting in /spl eta//sup d/=1.1 W/A for 64/spl times/2000 /spl mu/m/sup 2/ uncoated devices. We obtain total output powers /spl ges/3.2 W (qCW) and /spl ges/1.5 W (CW) at 20/spl deg/C.