深亚微米光学光刻工艺技术

光学光刻的生命力仍然在不断延续 ,即使在 0 13 μm及 0 13 μm以下集成电路制造水平上 ,光学光刻仍然是一个非常重要的候选者。深亚微米光学光刻工艺技术目前面临着越来越严重的挑战。对深亚微米光学光刻中的一些关键工艺技术如移相光刻、光学邻近效应校正、远紫外光刻胶、套刻对准误差等进行了论述。     

深亚微米光学光刻设备制造技术

相对于其它“后光学”光刻技术 ,在 0 1 3μm甚至 0 1 3μm以下集成电路制造水平上 ,光学光刻仍然具有强大的吸引力。随着光学光刻极限分辨率的不断提高 ,当代光学光刻设备正面临着越来越严重的挑战。论述了深亚微米光学光刻设备的技术指标和面临的技术困难 ,对其中一些关键的技术解决方案进行了分析。     

Advanced lithography for ULSI

Lens technology has advanced to the point where lithographic feature sizes equal to, or even smaller than, the wavelength of the light used in the stepper can be achieved in production. How far optical lithography can go from here depends both on how short a wavelength is possible and how close we can come to the absolute limit of diffraction. In this article, we will examine the current thinking on these questions, and discuss what might happen if and when optical lithography really can no longer be used     

Low voltage high performance E/D MOS logic

The letter describes a high performance MOS technology which produces both enhancement- and depletion-mode devices on the same substrate without using ion implantation. The enhancement mode devices, with 1?2 ?m channel lengths, can be realised using regular optical lithography and simple processing techniques.     

A little light magic [optical lithography]

At first glance, it appears that optical lithography has hit a dead end. Wavelengths shorter than 193 nm can't be used without a drastic redesign of lithographic systems because the shorter wavelengths are simply absorbed by the quartz lenses that direct the light onto the wafer. So is this the end? Not quite. There are a few more tricks that IC manufacturers can play. Lumped together, they are called resolution enhancement techniques (RETs), and in one way or another, they all coax the light into resolving shapes much smaller than its wavelength. The main techniques are optical proximity correction, phase-shifting masks, and modified, or "off-axis," illumination. With these tricks, the existing-and already paid for-optical lithography equipment can create patterns much smaller than the wavelength of the light used to produce them, these techniques can be easily extended to one-eighth the wavelength of the light-that is, to less than 25 nm for 193 nm light. Using these techniques, scientists at the Massachusetts Institute of Technology's (MIT's) Lincoln Laboratory, in Lexington, have built prototype transistors with a gate length of only 9 run-smaller than the smallest virus. Other tricks can also come into play. For example, by immersing the focusing lenses in a liquid with an index of refraction greater than that of air, optical lithography may be extended indefinitely. Ever since the 180 nm generation of devices, in 1999, RETs are making advanced optical lithography possible.     

下一代曝光(NGL)技术的现状和发展趋势

通过介绍光刻技术的演变和所面临的挑战 ,揭示下一代光刻技术的发展潜力和研究现状。通过比较几种具有较大潜力的NGL(浸没式ArF光刻机、极紫外光刻和电子束曝光 )的特点、开发现状和有待解决的关键技术 ,预言将来可能是以极紫外光刻、电子束曝光和某种常规光刻机结合的方式来实现工业、前沿科学技术需要的各种微米 /纳米级图形的制备。     

分子尺寸器件与单分子器件

未来的计算机可以小到什么程度?迄今无人可以做详尽的回答。但毫无疑问,硅基集成电路由于光刻技术的限制和生产成本随尺寸变小作指数增长,将很快达到它的极限(最小线宽100nm)。目前国际上已提出未来的纳米电子器件的各种方案,其中最小的器件有可能由单个分子所构成。扼要讨论了当前最“热门”的分子尺寸电子器件以及将要进一步发展的单分子电子器件。其中具有电双稳性能的分子是最可期许的材料。初步的研究结果表明能得到构成逻辑门用的单分子开关、超高密度存贮器和单分子整流器等功能器件的原型。最后还讨论了分子电子学进一步发展的前景和问题。     

应用于PHEMT器件的深亚微米T形栅光刻技术

PHEMT器件和基于它的高频单片集成电路广泛应用于现代微波/毫米波系统。当PHEMT器件的栅长缩短到足够短的时候,沿着栅宽方向的寄生电阻会影响PHEMT器件的性能。为了解决这个问题,一种具有大截面面积而底部长度却很小的T形栅结构通常被用于制作PHEMT器件,因为这种结构可以有效地减少由于栅寄生电阻而引起的晶体管噪声。对几种常用的制作深亚微米T形栅的三种光刻技术即光学光刻、电子束光刻、X射线光刻技术进行了比较分析。对于光学光刻技术,通常需要采用移相和光学邻近效应校正技术,它的制作成本低,但是很难用于制作深亚微米T形栅;对于电子束光刻技术,通常需要采用高灵敏度和低灵敏度的多层胶技术,虽然它的栅长可以制作到非常小,但是它的生产成本非常高,而且它的生产效率非常低;对于X射线光刻技术,它不仅可以用于制作深亚微米T形栅,而且它的生产效率非常高,T形栅的形状可以非常容易控制。     

无机激光热刻蚀材料的研究进展

激光热刻蚀技术是近年发展起来的利用激光热刻蚀薄膜的热变化阈值特性突破光学衍射极限进行纳米图形制备的新技术,在亚波长纳米结构器件和高密度光盘母盘制造等领域具有广阔的应用前景.阐述了激光热刻蚀技术的基本原理和特点,以及对激光热刻蚀材料性质的要求,综述了相变型激光热刻蚀薄膜材料(包括硫系相变薄膜材料、金属亚氧化物薄膜材料和陶...     

Limits of lithography

Lithography technology has been one of the key enablers and drivers for the semiconductor industry for the past several decades. Improvements in lithography are responsible for roughly half of the improvement in cost per function in integrated circuit (IC) technology. The underlying reason for the driving force in semiconductor technology has been the ability to keep the cost for printing a silicon wafer roughly constant while dramatically increasing the number of transistors that can be printed per chip. ICs have always been printed optically with improvements in lens and imaging material technology along with decreases in wavelength used fueling the steady improvement of lithography technology. The end of optical lithography technology has been predicted by many and for many years. Many technologies have been proposed and developed to improve on the performance of optical lithography, but so far none has succeeded. This has been true largely because it has always been more economical to push incremental improvements in the existing optical technology rather than displace it with a new one. At some point in time, the costs for pushing optical lithography technology beyond previously conceived limits may exceed the cost of introducing new technologies. In this paper the author examines the limits of lithography and possible future technologies from both a technical and economic point of view     

采用方形照明提高分辨率和焦深

:随着光学光刻技术向更小特征尺寸加工推进 ,必然要重视提高分辨率的方法。通过强、弱离轴方法的照明变形技术正引起极大的关注。特别是研究x、y定向的特征尺寸 ,照明分布形状可不一定是圆形的。介绍了采用直角特性的照明形状可提高成像质量。讨论了方形照明的用途 ,并确定了它与光学邻近校正 (OPC)、像差及其它成像因素的关系。     

侧墙铬衰减型新结构移相掩模的应用

提出了一种全新的移相掩模--侧墙铬衰减型移相掩模（SCAPSM) ，相对于通常的衰减型移相掩模，其制造工艺仅多两步，却可以较大幅度提高光刻分辨率. 采用PROLITH光学光刻模拟软件，参考ArF步进扫描投影光刻机TWINSCAN XT:1400E的曝光参数，对侧墙铬衰减型移相掩模的工艺进行了研究，证明SCAPSM+离轴照明的方案可以将干式193nm光学光刻的分辨率提高到50nm.     

浸没式光刻向22nm挺进

简述了光学光刻技术在双重图形曝光、高折射率透镜材料及浸没介质、32nm光刻现状及22nm浸没式光刻技术的进展,指出了光学光刻技术的发展趋势及进入22nm技术节点的前景。     

采用梯形棱镜波前分割的激光干涉光刻技术

光学光刻技术在微细加工和集成电路(IC)制造中一直是主流技术。随着IC集成度的提高,要求越来越高的光刻分辨力,但光学光刻的分辨极限受光刻物镜数值孔径(NA)和曝光波长(λ)的限制。激光干涉光刻技术具有高分辨、大视场、无畸变、长焦深等特点,其分辨极限为λ/4,在微细加工、大屏幕显示器、微电子和光电子器件、亚波长光栅、光子晶体和纳米图形制造等领域有广阔的应用前景。阐述了激光干涉光刻技术的基本原理。提出了一种采用梯形棱镜作为波前分割元件的激光干涉光刻方法。建立了相应的曝光系统,该系统可用于双光束、三光束、四光束和五光束等多光束和多曝光干涉光刻。给出了具有点尺寸约220nm的周期图形阵列的实验结果。     

Enhanced resolution for future fabrication

We have developed resolution-enhanced optical lithography processes that have enabled us to fabricate devices with deep sub-100 nm feature sizes. Isolated gate features were resolved down to 40 nm in resist using optimized phase-shift lithography processes. The addition of a small reactive ion etch (RIE) etch bias allowed us to fabricate transistors with gate lengths in the range 9-25 nm. This was achieved using standard 248 nm optical stepper, photoresist, and RIE technology. The capability is valuable for providing robust fabrication processes for advanced device technology studies. Double-exposure phase-shift imaging is also achieving growing industry acceptance with promising new results recently reported by UMC and Intel. These results show that optical lithography with aggressive resolution enhancements will likely be able to meet the needs of the semiconductor industry for the rest of this decade, pushing out the anticipated introduction of next-generation lithography (NGL) technologies further into the future.     

Optical requirements for projection lithography

An image modulation criterion is proposed as a simple optical performance parameter for lithography using positive photoresist. The modulation, or contrast, is defined in terms of the maximum and minimum intensity in the image of a line/space pattern as (I_MAX ? I_MIN)/(I_MAX + I_MIN). For lithography directly on integrated circuit wafers, a contrast in the range of 80–90% gives acceptable linewidth control. Universal curves are derived showing image contrast for diffraction-limited optical systems with partially coherent illumination and including defocus error. The allowable defocus is derived as a function of the contrast requirement and pattern linewidth. Based on these optical considerations, and the properties of positive photoresists, the useful resolution of state-of-the-art projection systems are shown to be in the neighborhood of 1.25 μm, and progress to a useful resolution of about 0.5 μm is forseeable.     

高数值孔径光刻中衬底反射率的控制

高数值孔径（NA）光刻中,需要控制衬底反射率以减小薄膜干涉对光刻性能的影响。采用薄膜光学方法研究了高NA光刻中底层抗反膜（BARC）对衬底反射率的控制。针对硅基底对单层和双层BARC进行优化以探索满足高NA光刻要求的BARC材料光学参数容限。结果表明,当NA超过0.8时,单层BARC无法控制衬底反射率而有必要采用双层BARC。横电（TE）比横磁（TM）偏振光的衬底反射率更难以控制。NA越大,单层BARC折射系数的优化值越大。双层BARC中的顶层膜应采用低吸收率材料而底层膜应采用高吸收率材料。本研究可为高NA光刻中的BARC材料研制及衬底反射率控制提供理论依据。     

ASML公司光学光刻技术最新进展

荷兰ASML公司作为全球三大光刻机集成生产商之一，通过不断的技术创新，在全球光刻机市场上居于领先地位。在简单介绍光刻机基本工作原理和主要技术指标的基础上，详细分析了ASML公司在光学光刻技术方面的最新技术进展。     

硅集成电路光刻技术的发展与挑战

从微电子集成电路技术发展的趋势,介绍了集成电路技术发展对光刻曝光技术的需求,综述了当前主流的DUV光学曝光技术和新一代曝光技术中的157nm光学曝光、13nm EUV曝光、电子束曝光、X射线曝光、离子束曝光和纳米印制光刻技术的发展状况及所面临的技术挑战.同时,对光学曝光技术中采用的各种分辨率增强技术如偏轴照明(OAI)、光学邻近效应校正(OPC)、移相掩膜(PSM)、硅片表面的平整化、光刻胶修剪(resist trimming)、抗反射功能和表面感光后的多层光刻胶等技术的原理进行了介绍,并对不同技术时代可能采用的曝光技术作了展望性的评述.     

衍射干涉光刻研究

光刻就是将掩模版上的图形转移到基底的过程,广泛应用于微电子、微机械领域。衍射现象是光刻工艺无法避免的问题,当掩模图形尺寸接近光源波长时,就会产生衍射干涉现象。利用这一现象,可以产生小于掩模图形尺寸的图形。采用严格耦合波分析算法对光刻过程中的衍射干涉做了仿真分析;并用karl suss MA6光刻机实现了基于掩模的干涉光刻实验,通过增加滤光片得到相干光源,增强光刻过程的衍射,形成衍射干涉,掩模版透光区域和部分不透光区域下方的光刻胶得到曝光,利用微米尺度的光栅图形,在光刻胶上产生亚微米的光栅;最后利用干法刻蚀工艺,在硅基底上加工出亚微米尺度光栅。