An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR

A 14-bit low power self-timed differential successive approximation(SAR) ADC with an on-chip multisegment bandgap reference(BGR) is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3 ppm/℃and a thermal drift of about 100μV over the temperature range of -40 to 120℃is implemented to provide a high precision reference voltage for the SAR ADC.The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system.Self-timed bit-cycling is adopted to enhance the time efficiency.The 14-bit ADC was fabricated in a TSMC 0.13μm CMOS process. With the on-chip BGR,the SAR ADC achieves an SNDR of 81.2 dB(13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from -40 to 120℃.     

A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction

A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit 100 MS/s SAR ADCs based on the proposed architecture with voltage-controlled delay lines based time-domain comparator is designed in a 65 nm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.81 dB (11.47 ENOB), a spurious free dynamic range (SFDR) of 80.33 dB for a near Nyquist input at 100 MS/s, while dissipating 11 mW from a 1.2-V supply, giving a FOM of 38.8 fJ/Conversion-step.     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

一种10位50MS/s两级逐次逼近流水线混合型A/D转换器

本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器（pipeline SAR ADC）。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。     

一种基于CMOS工艺的异步数字斜坡ADC

设计了一个5位330 MS/s的异步数字斜坡模数转换器(ADC)。采用中芯国际55 nm工艺和Cadence Virtuoso软件,对电路进行设计和仿真。供电电源为1.2 V,改进后的延迟单元将延迟时间缩短到50 ps。另外,该电路中的比较器采用自动关闭方式,节省了功耗。输入电压峰峰值为0.4 V时,仿真得到信噪失真比(SNDR)为28.19 dB,有效位(ENOB)为4.39位,无杂散噪声动态范围(SFDR)为35.87 dB,信噪比(SNR)为31.47 dB。     

A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.     

一种基于VCM开关切换的12位20 MS/s SAR ADC

设计了一种12位、采样率为20 MS/s的逐次逼近型模数转换器(SAR ADC)。整体电路为全差分结构,采用了一种基于VCM开关切换的分段式电容阵列。同时,比较器结合了前置运放和动态锁存器,与异步时序相配合,实现了SAR ADC高速工作。此外,采样电路采用栅压自举技术,提高采样的线性度。芯片基于TSMC 180 nm 1P5M CMOS工艺设计。仿真结果表明,当采样率为20 MS/s时,SAR ADC有效位数为11.94 bit,无杂散动态范围为86.53 dBc,信噪比为73.66 dB。     

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

This paper presents a 7-bit 15 × interleaved SAR ADC that operates up to 3 GS/s, using 180 nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2 bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7 bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2 C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits) > 6.5-bit and SFDR (Spur Free Dynamic Range) = −52.8 dBc for a single SAR converter with sampling at 200 MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR = −45 dBc with sampling at 3 GS/s up to Nyquist frequency. This ADC consumes 150 mW at 1.8 V supply and achieves a Figure-of-Merit (FoM) of 700 fJ/conv-step.     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset,and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm × 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.     

A novel 8-bit 20-MS/s folded residue amplification based pipelined ADC

A novel circuit is proposed for pipelining of single-slope analog-to-digital converters (ADCs). A new input-to-residue transfer function (TF), called folded residue amplification TF, is proposed for implementing this structure. The proposed structure enables the use of single-slope sub-ADCs in low-power, small-area pipelined structures. The gain of each stage is provided by current mirrors. Based on proposed structure, an 8-bit 20-MS/s fully-differential folded residue amplification based pipelined ADC is designed and simulated in a 90 nm CMOS technology. Calculated ENOB is 7.4-bit with 240 μW power consumption.     

An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer

This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3 dB at 200 MS/s. It consumes 3.91 mW from a 1.2 V supply, including the reference buffer.     

A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DAC

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of?±?1.2LSB/?±?1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.

     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

基于比较器亚稳态抑制技术的8位320 MS/sSAR ADC

提出一种比较器亚稳态抑制技术,并将其应用于一个8位320 MS/s 的逐次逼近型模数转换器(SAR ADC)。该技术抑制了比较器在高速工作情况下可能出现的亚稳态现象,从而降低了比较器出现错误结果的概率。同时,提出一种转换时间复用技术,使ADC能在转换与采样模式之间快速切换。与传统技术相比,随着工艺角、电源电压和温度(PVT)的变化,ADC的采样时间会被最大化。基于65 nm CMOS工艺,设计了一种8位320 MS/s SAR ADC。芯片测试结果表明,在1 V电源电压下,功耗为1 mW,信号噪声失真比(SNDR)>43 dB,无杂散动态范围(SFDR)>53.3 dB。SAR ADC核的芯片面积为0.021 mm²,在Nyquist采样率下,优值为29 fJ/step。     

A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor–resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator’s common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process–voltage–temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm² resulting in area efficiency of 122.6 μm²/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.