一种高速帧同步和相位模糊估计的方法及其FPGA实现

提出仅依靠接收符号和本地同步码快速确定MPSK调制符号的帧同步,并同时估计其相位模糊值的计算方法,给出减少一半计算量的简化相关算法以及设定两个门限的方法,并分析该同步器的性能.详细设计能估计相位模糊值的高遣帧同步嚣的结构,通过FPGA实现验证算法在高达320 MSPS的8PSK符号速率时均可以有效工作.     

一种高速数传接收机的高效维特比译码结构设计

在高速数传接收机中,通常采用并行解调结构,解调后的数据以多路并行的方式送给译码单元,因此对应的译码也需采用相应的结构。本文设计了一种并行的维特比译码架构,降低现场可编程阵列(FPGA)器件的处理速率,以适应高速接收机的应用。     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

高速无线数据传输中的补码键控扩频调制

补码键控扩频调制在克服多径效应、抗频率选择性衰落及抗窄带干扰方面有着优异的性能.IEEE802.11b标准规定采用补码键控技术以达到11Mbps,5.5Mbps的数据传输速率.介绍了该技术中采用的码字及其结构,并详细地给出了其调制与解调的具体实现.     

用于高速无线数据通信的空时编码

在无线通信中,当采用多发送天线增加带宽效率时,空时编码可以提供分集增益和编码增益.本文介绍并比较了两种用于高速无线数据通信的空时编码空时格栅编码(STTC)和空时分组编码(STBC).     

High Data Rate Alamouti Code From Field Extension

Alamouti code is the only known Orthogonal Space Time Block Code (OSTBC) with rate-1. All other known orthogonal codes have rate less than unity. The orthogonal property of OSTBCs reduces the decoding complexity to a large extent. High data rate Space Time Block Codes for arbitrary number of transmit antennas were recently proposed based on Division Algebras. But these STBCs are not orthogonal. Therefore their decoding complexity is very high. In this paper we propose high data rate Alamouti codes from field extensions for two transmit antennas. Our codes have better coding gain than the both high rate codes from division algebra and the rate-1 Alamouti code. Vishwanath R was born in Hyderabad, India in 1982. He did his B.E. in Electronics and Communications Engineering from Birla Institute Of Technology, Ranchi, India in 2002 and Master of Technology in Communications Engineering in 2005 from Indian Institute of Technology Delhi, India.. Currently he is pursuing PhD from Indian Institute of Technology Delhi, India. His research interests include Routing in Optical Networks, Signal Processing, Wireless Communications and Image Processing. He is a member of the IEEE. Bhatnagar Manav R was born in Moradabad, India in 1976. He did his B.E. in Electronics in 1997 and Master of Technology in Communications Engineering in 2005 from Indian Institute of Technology Delhi, India. He has worked as lecturer in Moradabad Institute of Technology, Moradabad, India from 1998–2003. He is currently pursuing PhD from Indian Institute of Technology Delhi, India. His research interests include Routing in Optical Networks, Signal Processing in Wireless Communications and Image Processing. He is a member of the IEEE.     

Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs

This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the design process of complex systems, the design method incorporates a form of predictive analysis which can estimate the degree of contention in a given system without performing detailed simulation. This predictive analysis method is used to determine the minimum frequency of operation for generated topologies, and is incorporated into the topology generation process. The proposed design method was tested using real-word applications, including an MPEG4 decoder and a multi-window display application. The generated topologies were found to offer similar or better performance when compared with regular topologies. However, the topologies generated by our method were more economical, using, on average, half the network resources of regular topologies.     

High Data Rate OFDM System with Simplified DAPSK Demodulation

1IntroductionIn future wireless communication systems beyond3G,high data rate more than 2 Mbps is desired. TheInterSymbol Interference (ISI) resulted fromthe fre-quency-selective fading channel will be a crucial problemwhich may degrade system performance severely.OFDMis an effective technique to combat this adversecharacteristic[1 ~3],and has beenadoptedfor manystan-dards , such as DAB, DTVB, Hiperlan/2 and IEEE802 .11 ,etc .Spectrally efficient modulation schemes have also ab-sorbe…     

Channel Feedback Quantization for High Data Rate MIMO Systems

In this work, we study a multiple-input multiple-output (MIMO) wireless system where the channel state information is partially available at the transmitter through a feedback link. Based on singular value decomposition, the MIMO channel is split into independent sub-channels. Effective feedback of the required spatial channel information entails efficient quantization/encoding of a unitary matrix. We propose two schemes for quantizing unitary matrices via Givens rotations and examine the performance for a scenario where the rates allocated to the sub-channels are selected according to their corresponding gains. Numerical results show that the proposed schemes offer a significant performance improvement as compared to that of MIMO systems without feedback, with a negligible increase in the complexity     

高帧频CCD数据采集处理系统的设计

针对某高帧频CCD相机的设计要求,提出一种可行的CCD数据采集处理方法.由FPGA为CCD、A/D变换器提供控制信号,利用多通路数据传输的结构实现了高速图像数据的同步采样,并由高速A/D芯片AD9942实现数据的模/数转换.创新性地将控制信号和数据缓存集成在一片FPGA上,仿真结果能够很好地实现CCD高速数据采集处理.     

测控链路中高速OQPSK解调技术分析

根据实际工程需要,基于软件无线电的设计思想,分析了影响测控链路中解调性能的主要因素,提出了一种符号定时同步选用前馈式同步算法,载波同步选用反馈闭环结构的OQPSK解调器的实现结构。介绍了滤波抽取及复数下变频、符号定时同步和载波同步的详细设计与实现方法。通过将2.5⁸0 Msps的信号解调实测,并与理论数值对比,实测结果比理论值恶化少于1 dB。OQPSK解调器结构简单,具有高度的稳定性、灵活性和可扩展性等。     

CDMA200O中高数据传输速率的实现方法

介绍了CDMA2000中高速率的实现方法,对实现方法带来的好处和存在的问题进行了分析。最后对beyond3G的发展提出了自己的看法。     

地空高速数据链的关键技术

高速数据传输是地空数据链的发展趋势。当前器件的工作速度是高速应用的瓶颈,为了能在较低速度的器件上实现高速处理,必须根本性地改变算法结构,采用并行处理方式。并行结构会对解调器的时间同步和载波同步造成影响,需加以研究。为实现高速数据解调,提出了并行处理的解调器结构,研究了并行结构下的定时同步和载波同步方法,分析了克服符号间干扰的判决反馈均衡算法,探讨了抑制宽带信号中窄带干扰的自适应干扰对消方法。     

Energy Efficiency of Error Control for High Data Rate WPAN

This paper addresses the issue of energy efficiency for error control mechanisms over WPAN systems. An analytical formulation has been developed to study the trade-off between link layer performance and energy consumption for two types of error control schemes: pure ARQ and type II hybrid ARQ protocol. An MC-CDMA-based system is considered. First of all, the analysis has been used to compare different error recovery schemes from the energy efficiency point of view. Moreover, it has been found that, for any channel conditions, there exists an optimal value of the transmit power that maximizes the energy efficiency. The paper also shows how this result can be used to design the power control of an energy efficient CDMA-based communication system. Mauro De Sanctis received the “Laurea' degree in Telecommunications Engineering from the University of Roma “Tor Vergata' in 2002. He is currently a Ph.D. Student and Assistant Professor in the Department of Electronics Engineering of the same University. He is involved in the DAVID (DAta and Video Interactive Distribution) satellite mission of the ASI (Italian Space Agency); his research is funded by the ASI. He is also involved in the MAGNET (My personal Adaptive Global NET) European FP6 integrated project and in the SatNEx European network of excellence. He worked on Italian national research projects on satellite-terrestrial systems integration such as SHINES (Satellite and HAP Integrated NEtworks and Services) and CABIS (CDMA for Broadband mobile terrestrial-satellite Integrated Systems). On autumn 2004 he joined the CTIF (Center for TeleInFrastructure), a research center focusing on modern telecommunications technologies located at the University of Aalborg (Denmark). His main areas of interest are: integration of different satellite networks, stratospheric platforms and terrestrial networks in a multi-layered fashion, internetworking and resource management in satellite systems and energy efficiency of WPAN systems. Simone Quaglieri received the “Laurea' degree cum laude in Telecommunications Engineering from the University of Roma “Tor Vergata', Italy, in 2004. His thesis, concerning the study of an analytic model for the Raman amplifier in optical systems with high bit rate, has been developed in the same University. During 2002 he worked as stagiaire on the design and development of optical submarine systems at the Elettra company (Telecom Italia group, Italy). He is joining the IRIS (Innovative Radio Integrated Systems) group at the University of Roma “Tor Vergata' as Research Engineer, where he is working on MC-CDMA based technology in the frame of the MAGNET (My Adaptive Global NETwork) European project. He is also working on error recovery mechanisms over satellite systems, and his research is funded by the EC in the frame of the SatNEx (Satellite Network of Excellence) European project. Ernestina Cianca graduated cum laude in Electronics Engineering in 1997 at the University of L'Aquila. She was with Italtel/Siemens (L'Aquila) from 1997 to 1998. She got her Ph.D. degree from the University of Rome Tor Vergata (URTV). The thesis work was on power management in CDMA-based satellite systems. She has been employed by the University of Aalborg, Denmark, in the Wireless Networking Groups (WING), as Research engineer (2000–2001) and as Assistant Professor (2001–2003). In particular, from Sept. 2002 she has been Technical Manager of Aalborg University for the IST-STRIKE project. She is currently Assistant Professor in Telecommunications at the URTV (Dpt. of Electronics Engineering), teaching DSP, Information and Coding. Her research mainly concerns wireless access technologies (CDMA and MIMO-OFDM-based systems), in particular, Radio Resource Management at PHY/MAC layer, ARQ/HARQ, TCP-IP issues over wireless links, integration of terrestrial and satellite systems. She has been the vice-coordinator of the following national research programs: CABIS, on CDMA integrated mobile systems (2000-2002) and SHINES, on satellite-HAP integrated networks for multimedia applications co-financed by MIUR (2002–2004). She is currently working on various European Projects: EU FP6 IP MAGNET (My personal Adaptive Global NET); EU ASIA LINK EAGER-NetWIC (Euro-Asian Network for Strengthening Graduate Education and Research in Wireless Communications); EU Network of excellence NEXWAY. She is author of about 40 papers, on international journals/transactions and proceedings of international conferences. Marina Ruggieri graduated in Electronics Engineering in 1984 at the University of Roma. She was: with FACE-ITT and GTC-ITT (Roanoke, VA) in the High Frequency Division (1985–1986); Research and Teaching Assistant at the University of Roma Tor Vergata (URTV) (1986–1991); Associate Professor in Telecommunications at the University of L'Aquila (1991–1994). Since November 2000 she is Full Professor in Telecommunications at the URTV (Dpt. of Electronics Engineering), teaching DSP, Information and Coding. In 1999 she has been appointed member of the Board of Governors of the IEEE AES Society (2000–2002) and re-elected for the period 2003–2005. Her research mainly concerns space communications and navigation systems (in particular satellites) as well as mobile and multimedia networks. She is the Principal Investigator of: satellite scientific communications missions (DAVID, WAVE) of ASI; national research programs (CABIS) on CDMA integrated mobile systems (2000–2002) and on satellite-HAP integrated networks for multimedia applications (SHINES), co-financed by MIUR (2002–2004). She co-ordinates the URTV Unit in various European Projects: EU FP6 IP MAGNET (My personal Adaptive Global NET); EU ASIA LINK EAGER-NetWIC (Euro-Asian Network for Strengthening Graduate Education and Research in Wireless Communications); EU Network of excellence NEXWAY; GALILEO JU 1st Call – July 2003: VERT (VEhicular Remote Tolling); and in the ASI program on V-band payloads (TRANSPONDERS). She is member of the Editorial Board of Wireless Personal Communications – an International Journal (Kluwer). She was awarded the 1990 Piero Fanti International Prize and she had a nomination for the Harry M. Mimmo Award in 1996 and the Cristoforo Colombo Award in 2002. She is author of about 170 papers, on international journals/transactions and proceedings of international conferences, book chapters and books.     

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for processing computationally-intensive and energy-constrained workloads. The GALS methodology simplifies clock tree design, provides opportunities to use clock and voltage scaling jointly in system submodules to achieve high energy efficiencies, and can also result in easily scalable clocking systems. However, its use typically also introduces performance penalties due to additional communication latency between clock domains. We show that GALS chip multiprocessors (CMPs) with large inter-processor first-inputs–first-outputs (FIFOs) buffers can inherently hide much of the GALS performance penalty while executing applications that have been mapped with few communication loops. In fact, the penalty can be driven to zero with sufficiently large FIFOs and the removal of multiple-loop communication links. We present an example mesh-connected GALS chip multiprocessor and show it has a less than 1% performance (throughput) reduction on average compared to the corresponding synchronous system for many DSP workloads. Furthermore, adaptive clock and voltage scaling for each processor provides an approximately 40% power savings without any performance reduction. These results compare favorably with the GALS uniprocessor, which compared to the corresponding synchronous uniprocessor, has a reported greater than 10% performance (throughput) reduction and an energy savings of approximately 25% using dynamic clock and voltage scaling for many general purpose applications.      

Performance Analysis of High Data Rate MIMO Systems in Frequency-Selective Fading Channels

The performance of multicode direct-sequence spread-spectrum multiple-input multiple-output (MIMO) systems in the presence of frequency-selective fading is evaluated. We derive the asymptotic distribution of the multiple-antenna interference when the processing gain is sufficiently large. The probability of error is derived for the conventional RAKE receiver, and its performance is compared for various system configurations. We consider system tradeoffs for both fixed rate and fixed diversity. For a fixed total data rate, we demonstrate the advantage of decreasing the number of transmit antennas while increasing the number of codes, and for a fixed total diversity order, we demonstrate the advantage of decreasing the number of RAKE taps while increasing the number of receive antennas.      

高速数据率(HDR)的功率控制技术

HDR(high data rate,高速数据率)是面向CDMA2000所开发的高速无线接入技术,它可以在以传输电话语音为主的通道以外,引进可以满足高速数据通信需求的技术.在HDR系统中,由于前向功率恒定,不存在功率控制的问题.功率控制主要指的是反向功率控制,包括开环功率估计和闭环功率校正.本文集中对HDR系统里面的信道系统、反向功率控制、功率校正等几个关键技术进行了深入的研究.     

利用中继提高小区高数据速率覆盖的研究

利用中继将传统蜂窝网络中基站到移动台的直接链路拆分成两跳或多跳,能够有效地克服路径损耗和阴影衰落的影响,从而提高小区高数据速率覆盖范围。对比分析在蜂窝网络中引入固定中继和移动中继2种形式,可以得出当小区中的用户随机分布并且用户数较多时,采用移动中继较为合适;在用户数较少或者用户服从均匀分布时,则应采用固定中继。     

Resource Allocation in High Data Rate Mesh WPAN: A Survey Paper

IEEE 802.15.3 High data rate wireless personal area networks (HDR WPANs) have been developed to communicate with devices within 10 m at high speed. A mesh network made up of a parent piconet and several child piconets can support multi-hop communications. Wireless mesh networks (WMNs) have been expected to be the ultimate solution for the next decade wireless networking, showing rapid progress and many new inspiring applications. The international standardization organizations formed working groups to address the problem of standardization for WMNs. These groups were the IEEE 802.15.5 (mesh extensions for WPANs),the IEEE 802.11s (mesh extensions for WLANs), and the IEEE 802.16a (mesh extensions for WiMAX). The IEEE 802.15.5 standard is the standard which defines specifications for including multi-hop functionality in the legacy 802.15.3 and 802.15.4 low data rate (LDR) WPAN networks. The impetus for a WPAN to operate in a mesh topology is to increase the network coverage without increasing the transmit power, to increase the route reliability via route redundancy, self-configuration, and efficient use of device battery life. In the case of meshed WPANs, multiple WPAN clusters compete for channel time in a shared superframe. Therefore, it is essential to determine the channel time requirements of each cluster with a certain number of devices and to determine how these clusters can compete to the shared channel time. In this paper, we investigate the different resource allocation mechanisms related to the meshed HDR WPANs for the 802.15.3 and the 802.15.5 standards. We introduce the single hop and the multi-hop IEEE 802.15.3 WPAN architectures. This is followed by the introduction of the IEEE 802.15.5 standard that provides the mesh capabilities for extending the coverage area of HDR WPANs. The current on-going research issues for resource allocation, including beacon interference, reservation collision etc., in both meshed 802.15.3 and 802.15.5 are alluded to.     

一种可以高速传输数据的MTCM正交序列多码CDMA系统

为了有效地实现用户高速数据的传输本文提出了一种ＭＴＣＭ正交序列多码ＣＤＭＡ系统。这对此系统在ＡＷＧＮ信道的性能进行了计算,并和未编码系统的数值结果进行了分析和比较。