An input-free VT extractor circuit using atwo-transistor differential amplifier

A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V_T is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage     

Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

Investigation of SOI-like I-V characteristics fora 64-Mb DRAM SCC MOSFET with a buried drain

The MOSFET structure of a surrounding-high-capacitance cell (SCC) trench cell with a buried drain scaled down for 64-Mb DRAM applications has been studied using the device simulator MINIMOS. For this cell design, the depletion zones of the buried drain can pinch off the substrate at a sufficiently high drain bias. The resulting floating substrate causes sharply increased avalanche carrier generation similar to (but more severe than) the kink effects found in SOI structures. These effects limit the utility of this structure for small-geometry DRAM structures. The mechanism for the enhanced avalanche generation and its dependence on bias conditions and geometry have been studied, and pertinent design rules for punchthrough and pinchoff by the buried drain have been established     

High-performance Ka-band and V-band HEMTlow-noise amplifiers

Quarter-micron-gate-length high-electron-mobility transistors (HEMTs) have exhibited state-of-the-art low-noise performance at millimeter-wave frequencies, with minimum noise figures of 1.2 dB and 32 GHz and 1.8 dB at 60 GHz. At Ka-band, two-stage and three-stage HEMT low-noise amplifiers have demonstrated noise figures of 1.7 and 1.9 dB, respectively, with associated gains of 17.0 and 24.0 dB at 32 GHz. At V-band, two stage and three-stage HEMT amplifiers yielded noise figures of 3.2 and 3.6 dB, respectively, with associated gains of 12.7 and 20.0 dB and 60 GHz. The 1-dB-gain compression point of all the amplifiers is greater than +6 dBm. The results clearly show the potential of short-gate-length HEMTs for high-performance millimeter-wave receiver application     

Nonlinear parasitics in MODFETs and MODFET I-Vcharacteristics

A large-signal analysis of the source and drain resistance of MODFETs is reported. Velocity saturation in the two-dimensional electron gas (2DEG) and hypothetical rectifying effects in the n⁺-AlGaAs-i-GaAs interface are accounted for. Rectifying effects are found to be either absent or negligible. Current limitations in the 2DEG lead to the observed compression of the transconductance at large gate voltages, and an improved fit of the MODFET I-V characteristics is demonstrated using an approximate analytic formulation of the current-limited parasitic resistance. The high-frequency dependence of the source and drain resistance is also reported. A decrease of the source impedance for frequencies increasing from 1-30 GHz is predicted and can reach 30%, depending on the device structure. Such a frequency decrease of the parasitics is consistent with the reported increase of the effective transconductance of MODFETs at microwave frequencies. The reported frequency and current-limited parasitic models rely on parameters that can either be measured or calculated and are therefore appropriate for CAD applications     

New techniques for high-frequency RMS-to-DC conversion based on amultifunctional V-to-I convertor

Two bipolar RMS-DC convertor circuits of the computing type which require no rectifier function are discussed. Improved frequency response is thus obtained. RMS-to-DC computation is carried out in the current domain. To make the circuit suitable for voltage driving, a dedicated V-to-I convertor is developed. Measured 1% bandwidths of the RMS-to-DC convertors are 35 and 22 MHz, respectively. Conversion error is less than 1% for the crest factors up to five     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

Electrochemical C-V profiling of heterojunctiondevice structures

Electrochemical capacitance-voltage profiles of multiple (In,Al) GaAs heterostructures have been measured and compared with the results of a numerical calculation of the apparent charge density based on a one-dimensional Poisson solver. The calculation, using layer thicknesses, dopings, and heterojunction band discontinuities obtained from MBE growth calibrations, is in overall agreement with the measured data. The largest discrepancy occurs between the expected and measured heterojunction band discontinuity. This difference is consistent with an electrolyte/semiconductor interface which is not planar on a scale comparable to the layer thickness     

Phase noise reduction in a gyroklystron amplifier

A fast feedback loop is employed to reduce conventional phase fluctuation in a klystron and a gyroklystron using both proportional and proportional-integral type feedback circuits. Phase fluctuation of less than one degree is achieved in both the klystron and gyroklystron by using a proportional type feedback circuit; in the klystron, 1.8 degrees of phase jitter is reduced to 0.8 degrees and in the gryroklystron 1.9 degrees to 0.9 degrees. These results agree well with theory. A superior phase jitter reduction ratio of approximately 0.3 is demonstrated in both the klystron and gyroklystron by adding an integrating circuit.     

DC I-V characteristics of field emitter triodes

A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current I_FN. Based on these observations, a simple model has been developed to calculate the I-V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from I_c=I_FN-I_g as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Input I-V and sampling time characteristics ofthe ACT device

The input I-V and sampling-time characteristics of the acoustic charge transport (ACT) device are presented for ohmic-contact charge injection and Schottky-gate-modulated charge injection. A computationally efficient analysis technique is developed to calculate the I-V and sampling-time data from two-dimensional potential and carrier-density distributions. Device physics and architecture are incorporated into the analysis through a numerical charge-injection model which is used to compute the potential and carrier-density distributions. Theoretical results are presented to demonstrate the charge injection characteristic of some typical device structures. The effects that the injection method, the epitaxial layer structure and the acoustic wave amplitude have on device performances are discussed. The physical basis of the analysis enables it to be used to study several other design parameters. Experimental measurements of a device I-V and input transconductance show good agreement with calculated data. This analysis technique provides a means of assessing the performance potential of new device designs     

Near-ideal I-V characteristics of GaInP/GaAsheterojunction bipolar transistors

GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6-μm×6-μm and 100-μm×100-μm devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1×10^-6 A/cm². For the 6-μm×6-μm device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness     

High-power V-band AlInAs/GaInAs on InP HEMTs

The DC and RF performance of δ-doped channel AlInAs/GaInAs on InP power high-electron-mobility transistors (HEMTs) are reported. A 450-μm-wide device with a gate-length of 0.22 μm has achieved an output power of 150 mW (at the 1-dB gain compression point) with power-added efficiency of 20% at 57 GHz. The device has a saturated output power of 200 mW with power-added efficiency of 17%. This is the highest output power measured from a single InP-based HEMT at this frequency, and demonstrates the feasibility of these HEMTs for high-power applications in addition to low-noise applications at V -band     

A new technique to determine the average low-field electronmobility in MESFET using C-V measurement

A method to determine the average low-field mobility using the number of electrons available for the conduction based on C-V measurement is proposed. This technique requires neither information of the doping profile in the channel, nor the exact value of the threshold voltage. For a D-mode MESFET, the average electron mobility magnitude is compared with that of the C. Chen and D.K. Arch (1989) method. The technique to determine the average electron mobility in the channel described is much simpler. Based on C- V measurement, good agreement is obtained between experimental data and simulation calculation for the electron density in the channel. Using the proposed method, the dependence of average electron mobility on the gate voltage is also proposed. Using the proposed method for determining the average electron mobility, the effect of a p-buried layer on the mobility was investigated, and is in good agreement with the physical phenomena     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

An analytical model for I-V and small-signalcharacteristics of planar-doped HEMTs

An analytical current-voltage (I-V) model for planar-doped HEMTs is developed. This compact model covers the complete range of I-V characteristics, including the current saturation region and parasitic conduction in the electron-supplying layer. Analytical expressions for the small-signal parameters and current-gain cutoff frequency are derived from the I-V model. Modeling results for a 0.1-μm-gate planar-doped AlInAs-GaInAs HEMT show excellent agreement with measured characteristics. Threshold voltages and parasitic conduction in planar-doped and uniformly doped HEMTs are also compared and discussed     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

Modeling the gate I/V characteristic of a GaAsMESFET for Volterra-series analysis

The authors show that the Taylor-series coefficients of a FET's gate/drain I/V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I/V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained