Reduced oxide charge trapping and improved hot-electron reliabilityin submicrometer MOS devices fabricated by titanium salicideprocess

The effects of the titanium salicide (self-aligned silicide) process on the reliability of very-thin-gate-oxide MOSFETs have been studied. It is shown that the titanium salicide process, as compared to the conventional poly-Si gate process, has reduced electron and hole trapping in the oxide and improved hot-electron reliability. It is shown that these phenomena are related to the reduced hydrogen content in the oxide as revealed by a secondary ion mass spectrometry (SIMS) analysis     

Cyclic current-voltage characterization applied to edge damageevaluation in gate definition plasma etching

A simple two-terminal cyclic current-voltage (I-V) measuring approach is used to monitor damage in gate definition plasma etching of poly-Si gate 70 Å oxide MOS structures. This new technique is used to identify the presence of trapping and near-surface silicon substrate generation lifetime changes due to edge exposure     

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

The dielectric degradation phenomena in gate oxides of MoSi²/thin n⁺poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi², and the SEM or TEM observations of textures of MoSi², poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi²deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi²/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi²deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi²were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.     

Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

Post poly-Si gate rapid thermal nitridation for boron penetrationreduction and oxide reliability improvement

Boron penetration from p⁺ doped poly-Si gates in PMOSFET is greatly reduced by post poly-Si gate rapid thermal nitridation. Gate oxide reliability against boron penetration is significantly enhanced. When post poly-Si nitridation is combined with N ₂O annealed gate oxides, gate oxide charge-to-breakdown is markedly improved     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

Suppression of boron penetration for p+ stacked poly-Sigates by using inductively coupled N2 plasma treatment

Nitridation of stacked poly-Si gates by inductively coupled N₂ plasma (ICNP) treatment has been shown to suppress boron penetration and improve gate oxide integrity. The ICNP treatments on the stacked poly-Si layers create nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, positioning of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability     

A new poly-Si TFT structure with air cavities at the gate-oxideedges

We propose a new poly-Si TFT structure employing air cavities at the edges of gate oxide in order to reduce the threshold voltage shift after electrical stress and to decrease the large leakage current. Due to the low dielectric constant of air, the air cavity behaves as a thick insulator reducing the vertical electric field near the drain, so that poly-Si region under air cavity acts as an offset. The new poly-Si TFT structure has been successfully fabricated by employing wet etching of the gate oxide followed by atmospheric pressure chemical vapor deposition (APCVD) oxide deposition. Our experimental results show that the leakage current is considerably reduced without decrease of the on-current and the device stability such as threshold voltage shift under high-gate bias is also improved     

Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2 V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.     

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Impact of gate stack process on conduction and reliability of 0.18 μm PMOSFET

Aim of this work is the investigation of the impact of gate stack process on conduction and reliability of NMOSFET and PMOSFET in 0.18 μm dual-gate technology. Different poly-Si gate depositions and annealing oxidations have been compared, showing a strong impact on conduction characteristics only in PMOSFET in inversion mode. The differences have been ascribed to the contribution of electron tunneling through interface states at the poly-Si/SiO₂ interface, whose density depends on the poly-Si grain dimension. STEM cross-sections have indeed shown completely different grain size depending on the gate stack technology. A significantly different reliability performance is found in correspondence.     

A new built-in screening methodology to achieve zero defects in the automotive environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring.     

Gate isolation after cobalt suicide processing

MOSFET test structures have been prepared with self-aligned suicide (“salicide”) contacts formed by reaction with a cobalt film. This communication describes studies of gate to source/drain leakage in several cobalt salicide lots. Electrical tests establish that the leakage occurs across the oxide spacers. Leakage contour maps resemble dry etching patterns. A mild oxidation treatment following the cobalt stripping etch reduces leakage currents. Cross sectional transmission electron microscopy reveals cobalt remnants on the spacer surfaces in the leaky samples. These and other observations lead to the conclusion that the leakage paths contain both residual cobalt and cobalt silicide, and that the latter originates from silicon deposited on the spacers during pre-metal sputter etching.     

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.