共查询到20条相似文献,搜索用时 62 毫秒
1.
Wei Zhao Seabaugh A. Adams V. Jovanovic D. Winstead B. 《Electron Device Letters, IEEE》2005,26(6):410-412
The influence of tensile mechanical stress on ultrathin oxide gate currents in advanced partially depleted silicon-on-insulator MOSFETs is reported. Strain is applied uniaxially, perpendicular to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. The gate currents of the n-channel and p-channel MOSFETS are found to change linearly and in opposite (opposing) directions as a function of uniaxial strain. The nMOS transistors generally exhibit a decrease with applied tensile strain, while the nMOS transistors show increasing gate current with strain. The observed dependences are consistent with a gate current controlled by direct tunneling and perturbed by stress-induced changes in the energy band structure. 相似文献
2.
Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices. 相似文献
3.
In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided. 相似文献
4.
Zupac D. Baum K.W. Kosier S.L. Schrimpf R.D. Galloway K.F. 《Electron Device Letters, IEEE》1991,12(10):546-549
The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain 相似文献
5.
6.
Tung-Sheng Chen Yu-Ren Huang 《Components and Packaging Technologies, IEEE Transactions on》2002,25(3):511-517
The influence of mechanical stress on metal-oxide-semiconductor (MOS) devices has been studied and analyzed for their applicability as in-situ sensors that are capable of measuring packaging induced and/or externally applied stress. Either compressive or tensile stress would alter the electrical characteristics of MOS devices in a regular pattern and that can be explained by substrate piezoresistivity. The regularity of electrical parameter variation of MOSFETs and the high sensitivity in correspondence with mechanical stress have made them very attractive as stress sensors since they may provide accurate and localized stress-state measurements. Through careful analysis, appropriate MOSFET-based sensors may be designed for proper on-site stress measurement in packaging and other stress detection applications. In addition, the mechanical stress also cause MOS devices to exhibit shorter lifetime that can be attributed to the occurrence of stress-induced charge-trapping sites in gate oxide. For MOSFETs utilized as stress sensors, the reliability issue related to mechanical stress has to be accounted and certain modification of stress-state extraction procedure will be needed to maintain valid stress measurement. 相似文献
7.
High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm2 . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability 相似文献
8.
The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100% 相似文献
9.
Cellere G. Larcher L. Valentini M.G. Paccagnella A. 《Electron Devices, IEEE Transactions on》2002,49(8):1367-1374
The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc. 相似文献
10.
This work reports the effects of drain impact ionization injection on the gate dielectric breakdown. Results show that due to the high energy hot carrier injection, the gate oxide can break down twice at a low oxide electric field (<1.2 MV/cm). The first breakdown occurs simultaneously with the drain avalanche breakdown whereas the second breakdown occurs beyond the drain breakdown. It is further identified that the first gate oxide breakdown is governed by the thermionic emission of hot electrons at low oxide fields (<1.0 MV/cm) and by the scattering processes at higher oxide fields. The second breakdown is attributed to the Fowler–Nordheim (F–N) tunneling. 相似文献
11.
Gate current injection into the gate oxide of MOSFETs with a split-gate (virtual drain) structure is examined. The split-gate structure is commonly encountered in flash EEPROM and CCDs. An important parameter characterizing the gate current injection is the ratio φ b/φi (where φb is the effective energy barrier for electron injection into gate oxide, and φi , is the impact ionization energy). Measurements of φb /φi at relatively constant vertical and lateral electric fields are reported. Through the use of a novel triple-gate MOSFET, the drain current as well as the lateral and vertical electric field at the point of injection were independently controlled during the measurements. The measured φb/φi showed a dependence on gate and drain biases not reported previously 相似文献
12.
Undoped silicon dioxide is compared to oxide in which trichloroethylene (TCE) was used during growth. The gate leakage currents in MOS transistors are examined. It is shown that a reduction in the leakage current occurs in TCE oxides. A novel measurement technique is employed to examine the gate leakage currents of the MOSFETs. 相似文献
13.
K. Chatty T. P. Chow R. J. Gutmann E. Arnold D. Alok 《Journal of Electronic Materials》2002,31(5):356-360
Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides.
While the field-effect mobilities were approximately 3–5 cm2/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm2/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved
threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized
MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed
oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample. 相似文献
14.
15.
The purpose of this paper is to present an extensive study of three 1200 V silicon carbide (SiC) Power MOSFETs in non-destructive, but leading to degradations, short-circuit operation. Unusually, as compared with equivalent device built on silicon, the damage signature is a significant gate current increase but the components are still functional. In order to find the damage location, non-destructive and destructive methods have been carried out. The results converge to a local gate oxide breakdown caused by the important electrical and thermal stress during short-circuit operation leading to different failure mechanisms depending on the device design. 相似文献
16.
Momose H.S. Ohguro T. Morifuji E. Sugaya H. Nakamura S. Iwai H. 《Electron Devices, IEEE Transactions on》2001,48(6):1136-1144
The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO2-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated 相似文献
17.
A modeling tool is presented that allows a complete analysis of a DC stress experiment without assuming the location and amount of trapped oxide charges and interface states. To describe the buildup of oxide damage, a semiempirical rate equation approach is outlined. A completely self-consistent calculation is presented of the time dependence of the DC stress experiment. This calculation monitors the amount and location of charges built up in the 2-D oxide region during the stress line. The model includes competing trap mechanisms such as the formation of interface states and fixed oxide traps. This permits consideration of n- and p-channel MOSFETs with the same model. The calculations are compared to DC stress measurements on n- and p-channel devices with gate lengths of 0.65 μm that are typical for 16-Mb DRAMs 相似文献
18.
In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide. 相似文献
19.
20.
N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current 相似文献