Thermal Nitridation of Si and SiO/sub 2/ for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO/sub 2/. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO/sub 2/ in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I-V, C-V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C -V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-dowm VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO/sub 2/ and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO/sub 2/-Si interfaces.     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

SiO/sub 2//AlGaN/InGaN/GaN MOSDHFETs

The characteristics of a novel nitride based field-effect transistor combining SiO/sub 2/ gate isolation and an AlGaN/InGaN/GaN double heterostructure design (MOSDHFET) are reported. The double heterostructure design with InGaN channel layer significantly improves confinement of the two-dimensional (2-D) electron gas and compensates strain modulation in AlGaN barrier resulting from the gate voltage modulations. These decrease the total trapped charge and hence the current collapse. The combination of the SiO/sub 2/ gate isolation and improved carrier confinement/strain management results in current collapse free MOSDHFET devices with gate leakage currents about four orders of magnitude lower than those of conventional Schottky gate HFETs.     

The application of polyimide/silicon nitride dual passivation to AlxGa1−xN/GaN high electron mobility transistors

PECVD silicon nitride passivation is quite frequently done at the end of AlGaN/GaN HEMT fabrication before substrate back-side lapping. However, the PECVD silicon nitride process is likely to produce pinholes in the passivation film. A very thick PECVD silicon nitride film may produce mechanical stress on the underlying device. Polyimide passivation has also been known to be effective for AlGaN/GaN HEMT and it can also serve as a stress buffer. However, polyimide can take up water while PECVD silicon nitride is a good diffusion barrier for water, etc. Thus it is expected that a dual PECVD silicon nitride/polyimide passivation will be a better choice than just a single layer of PECVD silicon nitride or polyimide. In this paper, we will demonstrate the application of a dual PECVD silicon nitride/polyimide passivation to AlGaN/GaN HEMT process.     

RF-MBE生长的高Al势垒层AlGaN/GaN HEMT结构

采用RF-MBE技术,在蓝宝石衬底上生长了高Al组分势垒层AlGaN/GaN HEMT结构.用三晶X射线衍射分析得到AlGaN势垒层的Al组分约为43%,异质结构晶体质量较高,界面比较光滑.变温霍尔测量显示此结构具有良好的电学性能,室温时电子迁移率和电子浓度分别高达1246cm2/(V·s)和1.429×1013cm-2,二者的乘积为1.8×1016V-1·s-1.用此材料研制的器件,直流特性得到了提高,最大漏极输出电流为1.0A/mm,非本征跨导为218mS/mm.结果表明,提高AlGaN势垒层Al的组分有助于提高AlGaN/GaN HEMT结构材料的电学性能和器件性能.     

Application of electron holography to the determination of contact potential difference in an AlGaN/AlN/Si heterostructure

Electron holography was applied to determine the contact potential differences in an AlGaN/AlN/Si heterostructure formed by metallorganic vapor phase epitaxy. Since mean inner potentials are generally different for different materials, their values before and after forming the junction were evaluated first, then the contact potential difference was obtained by subtracting the difference of the mean inner potentials before forming the junction from the corresponding difference after forming the junction. The contact potential differences thus obtained were consistent with a reported asymmetric nonlinear behavior in the current-voltage characteristics measured for a similar heterojunction diode.     

Indium out-diffusion from silicon during rapid thermal annealing

The out-diffusion of indium (In) from In-implanted silicon (Si) samples that includes bare Si, samples with an oxide-cap layer, nitride-cap layer, and nitride/oxide/Si sandwiched samples, is investigated. The dose loss of In with respect to different implant energies, doses, and soak times during rapid thermal annealing (RTA) is quantified. Experimental results of bare Si samples show that over 90% of In out-diffusion happens within 1 sec of soak time in the RTA process. In the capped samples, In rapidly diffuses through the oxide layer and stops at the nitride/oxide interface. In gets piled up at the interface of Si/oxide and oxide/nitride, and nitride very efficiently prevents In out-diffusion from the oxide layer out to the nitride layer. In addition, In gets more segregated in the Si surface in the presence of boron.     

A polycide gate electrode with a conductive diffusion barrierformed with ECR nitrogen plasma for dual gate CMOS

A simple diffusion barrier technology for polycide gate electrodes is presented. An extremely thin silicon nitride layer is formed by poly Si surface nitridation with ECR nitrogen plasma of only nitrogen gas and without substrate heating. The silicon nitride layer acts as an excellent barrier to impurity diffusion from polysilicon to silicide. It was found that barrier formation with ECR nitrogen plasma results in no fatal degradation in the MOS interface characteristics. This technology is very effective for making dual polycide gates inexpensively due to its simplicity and a good affinity with conventional ULSI fabrication processes     

The Effect of an Fe-doped GaN Buffer on off-State Breakdown Characteristics in AlGaN/GaN HEMTs on Si Substrate

An Fe-doped GaN buffer layer was employed in the growth of AlGaN/GaN high-electron mobility transistors (HEMTs) on Si substrates. In order to investigate the effects of an Fe-doped GaN buffer on OFF-state breakdown characteristics, HEMT devices with an Fe-doped GaN buffer on Si substrates were fabricated along with conventional devices utilizing an unintentionally doped GaN buffer on Si substrates. The device characteristics were compared. While HEMT devices with the conventional structure showed an extremely unstable OFF-state breakdown behavior due to punchthrough to the Si substrate, it was demonstrated that an Fe-doped GaN buffer layer on a Si substrate successfully suppressed the premature failure caused by Si-induced breakdown. As a result, the AlGaN/GaN HEMTs with an Fe-doped GaN buffer on Si substrates exhibited much more consistent and enhanced breakdown voltages, when compared with the conventional devices. Consequently, it is highly desirable that AlGaN/GaN HEMTs on Si substrates have an Fe-doped GaN buffer layer in order to achieve stable and robust OFF-state breakdown characteristics     

Low- and high-frequency capacitance of aluminum gallium nitride/gallium nitride heterostructures with interface traps

We have studied frequency dependence of capacitance properties of aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructures with interface traps at the AlGaN/GaN interface. We have shown that ability of charge in interface traps to respond to external measuring signal is responsible for the frequency dispersion of capacitance curves. The difference between capacitance curves measured at low and high frequencies in experimental structures is similar to the difference between simulated capacitances of the heterostructures with interface traps measured at low and high frequencies. At a high frequency when the charge in interface traps does not follow the measuring signal, the capacitance curves are only shifted in voltage compared to the curve of the structure without interface traps. But for low frequency a capacitance peak is observed. Interface traps hence contribute to experimentally observed capacitance dispersion.     

Flat GaN epitaxial layers grown on Si(111) by metalorganic vapor phase epitaxy using step-graded AlGaN intermediate layers

In this work, we report on the growth by metalorganic vapor phase epitaxy (MOVPE) of GaN layers on AlN/Si(111) templates with step-graded AlGaN intermediate layers. First, we will discuss the optimization of the AlN/Si(111) templates and then we will discuss the incorporation of step-graded AlGaN intermediate layers. It is found that the growth stress in GaN on high-temperature (HT) AlN/Si(111) templates is compressive, although, due to relaxation, the stress we have measured is much lower than the theoretical value. In order to prevent the stress relaxation, step-graded AlGaN layers are introduced and a crack-free GaN epitaxial layer of thickness >1 μm is demonstrated. Under optimized growth conditions, the total layer stack, exceeding 2 μm in total, is kept under compressive stress, and the radius of the convex wafer bowing is as large as 119 m. The crystalline quality of the GaN layers is examined by high-resolution x-ray diffraction (HR-XRD), and the full-width-at-half maximums (FWHMs) of the x-ray rocking curve (0002) ω-scan and (−1015) ω-scan are 790 arc sec and 730 arc sec, respectively. It is found by cross-sectional transmission electron microscopy (TEM) that the step-graded AlGaN layers terminate or bend the dislocations at the interfaces.     

Flicker noise of GaN-based heterostructure field-effect transistors with Si-doped AlGaN carrier injection layer

Aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure field effect transistors (HFETs) with and without Si-doped AlGaN layer were fabricated and investigated. HFETs with the Si-doped AlGaN carrier-injection layer show better DC performance, and the transconductance is 150 mS/mm. However, the HFETs with Si-doped AlGaN layer present the deviation from the 1/f noise at low frequency. The Lorentz shape was observed in the noise spectrum. It suggests that traps might be more pronounced in this kind of structure. Therefore, the DC characteristics of HFETs can be improved by the insertion of Si-doped AlGaN layer, but it can result in more low-frequency noise with the carrier-injection layer.     

SiGe/SiHBT异质界面与pn结界面的相对位移的影响

从模拟和实验两方面研究了SiGe/Si HBT发射结中pn结界面和SiGe/Si界面的相对位置对器件的电流增益和频率特性的影响.发现两界面偏离时器件性能会变差.尤其是当pn结位于SiGe/Si界面之前仅几十?就足以产生相当高的电子寄生势垒,严重恶化器件的性能.据此分析了基区B杂质的偏析和外扩对器件的影响以及SiGe/Si隔离层的作用.     

Hole and electron current transport inmetal-oxide-nitride-oxide-silicon memory structures

The carrier transport properties in metal-oxide (top oxide) nitride-oxide (tunnel oxide) silicon (MONOS) memory structures have been investigated in steady-state conditions under negative gate bias voltage. Carriers were separated into holes and electrons utilizing an induced junction of the p-channel MONOS transistors. Two-carrier transport is confirmed in the structure at negative gate polarity. It is found that the relatively thick top oxide acts as a potential barrier to the holes injected from the Si into the thin nitride. It is also found that a portion of the electrons injected from the gate at negative gate polarity recombine with the holes injected from the Si even in such a thin nitride and/or at the top-oxide/nitride interface     

Elevated-Temperature Annealing Effects on AlGaN/GaN Heterostructures

The effect of high-temperature annealing of undoped AlGaN/GaN heterostructures on different substrates was systematically studied between 1100°C and 1230°C. An AlN spacer layer was found to add stability to structures on sapphire substrates. AlGaN/GaN heterostructures on SiC substrates demonstrated excellent robustness for the temperature range studied, maintaining their mobility, sheet resistance, and sheet concentration values, even after annealing. A silicon nitride, SiN _x , capping layer was found to assist in minimizing surface roughness during annealing and maintaining the electrical characteristics of the heterostructures. AlGaN/GaN heterostructures on SiC substrates showed a 20% decrease in mobility for uncapped samples compared with SiN _x -capped samples.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

成核层形貌对AlGaN/GaN异质结晶体质量，表面形貌以及电学特性的影响

Nucleation layer formation is a key factor for high quality gallium nitride（GaN）growth on a sapphire substrate.We found that the growth rate substantially affected the nucleation layer morphology,thereby having a great impact on the crystal quality,surface morphology and electrical properties of AlGaN/GaN heterostructures on sapphire substrates.A nucleation layer with a low growth rate of 2.5 nm/min is larger and has better coalescence than one grown at a high growth rate of 5 nm/min.AlGaN/GaN heterostructures on a nucleation layer with low growth rate have better crystal quality,surface morphology and electrical properties.     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。