共查询到20条相似文献,搜索用时 31 毫秒
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Amit Chaudhry 《微纳电子技术》2011,48(6):357-364
研发了一种通过MOSFET的超薄栅氧化物分析直接隧穿电流密度的模型。采用Wentzel-Kramers-Brilliouin(WKB)近似计算了隧穿概率,利用清晰的表面势方程改进模型的准确性。在研究模型中考虑了Si衬底中反型层的量子化和多晶硅栅耗尽,还研究了多晶硅掺杂对栅氧化层隧穿电流的影响。仿真结果表明,栅氧化层隧穿电流随多晶硅栅掺杂浓度的增加而增加。该结论与已报道的结果相吻合,从而证明了该模型的正确性。 相似文献
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Mudanai S. Yang-Yu Fan Qiqing Ouyang Tasch A.F. Banerjee S.K. 《Electron Devices, IEEE Transactions on》2000,47(10):1851-1857
The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schroedinger's equation and allowing for wavefunction penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The tunneling currents predicted by this technique compare well with the WKB solution. Also for the first time investigation of the wavefunction penetration into gate stacks and their effects on quantization in the substrate has also been performed. For the same effective oxide thickness (EOT) the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-K dielectrics as gate insulators the interfacial oxide needs to be eliminated 相似文献
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Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in
present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide
interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions.
Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent
agreement with experimental results in the literature. 相似文献
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Ming-Jer Chen Kum-Chang Chao Tzuen-Hsi Huang Jyh-Min Tsaur 《Electron Device Letters, IEEE》1992,13(12):654-657
The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10-3 to 5×10-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n + inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n+ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage 相似文献
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Yang N. Henson W.K. Hauser J.R. Wortman J.J. 《Electron Devices, IEEE Transactions on》1999,46(7):1464-1471
Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage 相似文献
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Kuo-Nan Yang Huan-Tsung Huang Ming-Chin Chang Che-Min Chu Yuh-Shu Chen Ming-Jer Chen Yeou-Ming Lin Mo-Chiun Yu Jang S.M. Yu C.H. Liang M.S. 《Electron Devices, IEEE Transactions on》2000,47(11):2161-2166
A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO2-Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass moxh =0.51 Mo for the parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p+ poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing the oxide field down below 1 MV/cm 相似文献
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A simplified method to calculate the band bending and subband energy is presented to investigate the Quantum Mechanical Effects (QMEs) in MOS structure inversion layer. The method is fairly unique compared with the published methods in the reversed nature of the iteration procedure. It has high efficiency and good convergence characteristics. Gate capacitance in MOS structure inversion region is formulated in both quantum mechanical cases and semi-classical cases and Quantum Mechanical Effects on gate capacitance have been analyzed. Results of different substrate doping levels are compared and the substrate doping concentration dependence of QMEs on gate capacitance is studied. It is shown that QMEs lead to a substantial decrease in gate capacitance in the strong inversion region. Results of different substrate doping levels indicate that the QMEs on gate capacitance are different substantially in the threshold region at different substrate doping levels but almost the same in the strong inversion region. 相似文献
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A simple analytical model has been developed to study quantum mechanical effects (QME)in a germanium substrate MOSFET (metal oxide semiconductor field effect transistor),which includes gate oxide tunneling considering the energy quantization effects in the substrate.Some alternate high dielectric constant materials to reduce the tunneling have also been studied.By comparing with the numerically reported results,the results match well with the existing reported work. 相似文献
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《Solid-state electronics》2004,48(10-11):1801-1807
In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO2 and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO2 high-K dielectric (6.4 nm, Kf=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO2 film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages. 相似文献
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Hongyu Yu Yong-Tian Hou Ming-Fu Li Dim-Lee Kwong 《Electron Devices, IEEE Transactions on》2002,49(7):1158-1164
The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm2 and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm2 相似文献
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Detailed investigation of n-channel enhancement 6H-SiC MOSFETs 总被引:1,自引:0,他引:1
Basic MOSFET parameters like inversion layer mobility, threshold voltage, intrinsic mobility reduction factor and interface state density extracted from the subthreshold slope were examined in detail for 6H-SiC enhancement-mode n-channel MOSFETs. The inversion layer mobility and the threshold voltage were determined as a function of substrate doping concentration as well as device temperature. The interface state density was studied for different substrate doping concentrations. The inversion layer mobility was found to decrease strongly with increasing substrate doping. In contrast to earlier reports the inversion layer mobility decreases also with temperature. Furthermore, the threshold voltage depends more pronounced on substrate doping and temperature than theoretically expected. The interface state density extracted from the subthreshold slope increases significantly with substrate doping concentration. All these phenomena are consistently interpreted by the classical MOSFET behavior which is extended by acceptor like interface states. These states are located close to the conduction band and exhibit a density increasing drastically toward the band edge 相似文献
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Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs 总被引:1,自引:0,他引:1
《Electron Devices, IEEE Transactions on》2009,56(8):1667-1673
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The influence of the gate electrode p-polysilicon doping concentration on gate oxide breakdown data is investigated. It is shown that a small variation in doping concentration of p-doped polysilicon gates as well as an inversion layer in p-polysilicon gate strongly affects the results, if PMOS devices are stressed in inversion biasing mode by applying a constant current stress. 相似文献
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Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling 总被引:1,自引:0,他引:1
Jun-Wei Wu Jian-Wen You Huan-Chi Ma Chih-Chang Cheng Chang-Feng Hsu Chih-Sheng Chang Gou-Wei Huang Tahui Wang 《Electron Devices, IEEE Transactions on》2005,52(9):2061-2066
Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model. 相似文献
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The generation of interface traps in p-MOSFETs subjected to hot-electron injection is found to proceed even after the stress has been terminated. The extent of post-stress interface trap generation is strongly dependent on the magnitude of the preceding hot-electron stress, as well as the magnitude and polarity of the gate voltage during relaxation. Trap generation is enhanced for negative gate voltage anneal, but suppressed for positive gate voltage anneal. For a given stress-induced damage, the corresponding trap generation kinetics can be completely described by a single characteristic, which is shifted in time according to the magnitude of the applied gate voltage. Existing interface trap generation models are discussed in the light of the experimental results. A new model involving the tunneling of holes from the inversion layer to deep-level electron traps is proposed. Similar post-stress effect observed for hot-electron stressed n-MOSFETs provides additional support for the model. Our work suggests that near-interface electron traps, apart from the well-known hole traps, may also significantly affect the long-term stability of the Si-SiO2 interface 相似文献