新型基区结构高反压功率晶体管的优化

依据电参数指标要求,针对高压-高增益硅功率晶体管基区结构和终端结构进行优化研究。提出了一种可用于改善集电极-发射极击穿电压(V_(BRCEO))和电流放大倍数(β)矛盾关系的带埋层的新型基区结构,并针对埋层基区结构对高压-高增益硅功率晶体管电性能及可靠性的影响进行了研究。仿真结果表明:新型基区结构不仅可以很好地折中晶体管β与V_(BRCEO)之间的矛盾关系,而且还能在较大的埋层基区宽度、埋层基区掺杂峰值浓度范围内使晶体管获得较低且一致性较好的饱和压降;具有新型基区结构的晶体管在改善正偏的情况下抗二次击穿能力具有明显优势。由仿真得到的器件结构参数,研制出的样片的β,V_(BRCEO)和集电极-基极击穿电压(V_(BRCBO))均满足电参数指标要求。     

法国工程师制成超高速晶体管

法国国家电信研究中心的微电子研究所(CNET)内一支工程师队伍已成功地制成单块半导体-金属-半导体晶体管。早在二十多年前就提出用这种结构来代替常规的npn晶体管,自那时起,它一直困扰着研究者们。他们的成就是获得了用一层很薄的金属代替标准晶体管基区的器件。这样就避免了常规晶体管因基区电阻率造成的性能局限,大大缩短了电子从集电极到发射极的必要渡越时间。AT＆TBell实验室的研究人员计算过:对于优化的SMS晶体管,其理论截止频率应为30GHz左右,它甚至比GaAs器件的速度还快。从结构上讲,SMS晶体管简单得令人难以置信,钴的二硅化物薄层夹在二层较厚的硅层中。工作时,二个硅层分别作为晶体管的发射极与集电极,而把CoSi_2作为基区。     

用p埋层CMOS工艺制造横向磁敏晶体管

本文介绍了一种用P埋层CMOS工艺制造的横向磁敏晶体管(LMT)。器件结构是双基极、双集电极npn晶体管。它具有抑制侧向注入效应,即将注入集中于发射区的中部,在中性基区的少数载流子受到双重偏转作用,消除了横向无功电流。在CMOS工艺的基础上加了P埋层,消除了纵向无功电流。器件对磁场有良好的线性响应。     

集电极扩散隔/基极扩散隔离

集电极扩散隔离器件——在把双极集成电路大规模集成化时的最大障碍是隔离,这种结构的目的是尽可能减少隔离所需的面积。集电极扩散隔离(以后缩写成CDI)的特点是把集电极的引出区同时也作为隔离区使用。与过去的晶体管相比,有如下几个不同点: 1) 过去的集电极是使用n型外延生长层,而CDI只是使用n~+型扩散隐埋层。 2) 基区层过去是在集电极n型外延层上做P型扩散形成的,而在CDI结构中却是     

超高压SiGe HBT器件结构及制作工艺研究

介绍了一种超高压锗硅异质结双极晶体管(SiGe HBT)的器件结构及制作工艺。该器件增大了N型赝埋层到有源区的距离,采用厚帽层锗硅基区及低浓度发射区的制作工艺,以提高SiGe HBT的击穿电压;在基区和发射区之间利用快速热处理提高工艺稳定性,并使HBT的电流增益(β)恢复到原来水平,以弥补厚帽层锗硅基区及低发射区浓度造成的电流增益降低。基区断开时,发射区到集电区的击穿电压(BVCEO)提高至10V,晶体管特征频率达到20GHz。     

超增益硅MIS异质结发射极晶体管

描述了共发射极电流增益接近25000的硅双极晶体管,这个值被认为是曾报导过的双极器件电流增益的最大值。以一个隧道贯穿金属二薄绝缘体一半导体(MIS)接触连同一个浅注入基区为基础的异质结发射极结构是获得这种改进性能的主要原因。该结果的意义在于:它证明了在发射极的注入效率和可以导致在应用范围内改进硅双极晶体管性能的基区特性控制这两方面的优点。     

守得云开,FD-SOI工艺迎来爆发期

FD-SOI(全耗尽绝缘硅)是指一种平面晶体管结构。这种平面架构是通过在绝缘硅片晶圆超薄的绝缘氧化埋层(BOX)上再生长一层超薄的单晶硅层来实现的。由于采用超薄硅层,所以不需要沟道掺杂,使晶体管得以全耗尽。此外,薄氧化埋层使得基底偏压功能可以满足功耗/性能以及成本要求。相比传统的硅CMOS(bulk     

双极器件中硅基区和锗硅基区的禁带变窄量

采用一种新的方法计算双极器件中离子注 B硅基区和原位掺 B的锗硅基区禁带变窄量 .在器件基区的少子迁移率、多子迁移率和方块电阻已知的情况下 ,应用这种方法只需测量室温和液氮温度下的电学特性就可以获得禁带变窄量 .这种方法从双极晶体管的集电极电流公式出发 ,利用 VBE做自变量 ,在室温和液氮温度下测量器件的Gum mel图 ,选取 ln IC随 VBE变化最为线性的一部分读出 VBE及相应的 IC数值 ,获得两条 VBE- ln IC直线 ,通过求解两条直线的交点可以计算出基区的禁带变窄量ΔEG.利用这种方法测试了硅双极器件和锗硅基区双极器件 ,其基区禁带变窄量分别为     

锗硅HBT BiCMOS工艺中的p-i-n开关二极管设计

介绍了一种集成在BiCMOS工艺的p-i-n开关二极管的器件。它由在STI下面的n型赝埋层作为p-i-n的n区,锗硅npn异质结双极型晶体管的重掺杂外基区作为p-i-n的p区。同时新开发了穿过场氧的深接触孔工艺用于赝埋层的直接引出,并采用p-i-n注入用于对i区进行轻掺杂。借助半导体工艺与器件仿真软件,得到了有源区尺寸、赝埋层到有源区的距离、p-i-n注入条件等关键工艺参数对p-i-n性能的影响。最后优化设计的p-i-n二极管,其在2.4 GHz频率下的指标参数,如插入损耗为-0.56 dB,隔离度为-22.26 dB,击穿电压大于15 V,它达到了WiFi电路中的开关器件的性能要求。     

GSMBE生长In_(0.49)Ga_(0.51)P/GaAs HBT微结构材料及器件研究

采用 GSMBE技术 ,在材料表征和分析的基础上 ,通过优化生长条件 ,生长出高性能In0 .4 9Ga0 .51P/ Ga As异质结双极晶体管 (HBT)微结构材料 ,并制备出器件。材料结构中采用了厚度为 6 0 nm、掺杂浓度为 3× 10 19cm-3的掺 Be Ga As基区和 5nm非掺杂隔离层 ,器件流片中采用湿法化学腐蚀制作台面结构。测试结果表明该类器件具有良好的结特性 ,在集电极电流密度 2 80 A/cm2时其共发射极电流增益达 32 0。由此说明非掺杂隔离层的引入有效地抑制了由于基区 Be扩散导致的 pn结与异质结偏位及其所引起的器件性能劣化。     

Self-aligned Ti germanosilicide formation on a polycrystalline Si/SiGe/Si extrinsic base for SiGe heterojunction bipolar transistors

This work reports our investigation of a microstructure of self-aligned Ti germanosilicide made on polycrystalline Si/SiGe/Si multilayers. The existence of the SiGe layer restricted the growth of the Ti germanosilicide layer and produced protrusions penetrating the underlying polycrystalline layer. Each protrusion corresponded to a stacking-faulted single grain of the C49 phase. The microstructure of the thin Ti germanosilicide layer and the deep protrusions caused an increase of the sheet resistance and the contact resistivity of the extrinsic base region. The raised contact resistivity led to a degradation of radio frequency (RF) and noise characteristics of the SiGe heterojunction bipolar transistor (HBT).     

Selective silicon epitaxial growth on a submicrometer WSi2 grating: Application to the permeable base transistor

We report the silicon epitaxial growth on top of a tungsten disilicide grating using a rapid thermal processing, low pressure chemical vapor deposition reactor. The epitaxial growth of silicon is shown to proceed two dimensionally from the Si surface without reaction with the underlying WSi₂ grid. Both lateral diffusion over WSi₂ of Si adsorbed species and vertical diffusion of Si through the silicide film are shown to occur with respective weight depending on the width of the WSi₂ lines. This allows silicon selective growth on patterned Si/WSi₂ structure for grating periodicity below 1 μm. Preliminary electrical measurements of the Si/WSi₂/Si overgrown permeable base transistor (PBT) thus fabricated are presented, showing current densities J_max of up to 6000 A/cm² and transconductancesg _m of 5 mS/mm.     

Demonstration and properties of a planar heterojunction bipolartransistor with lateral current flow

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 μm. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-μm stripe     

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200 V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.     

Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Ultrathin strained-Si/strained-Ge heterostructures on insulator have been fabricated using a bond and etch-back technique. The substrate consists of a trilayer of 9 nm strained-Si/4 nm strained-Ge/3 nm strained-Si on a 400-nm-thick buried oxide. The epitaxial trilayer structure was originally grown pseudomorphic to a relaxed Si_0.5Ge_0.5 layer on a donor substrate. Raman analysis of the as-grown and final transferred layer structures indicates that there is little change in the strain in the Si and Ge layers after layer transfer. These ultrathin Si and Ge films have very high levels of strain (∼1.8% biaxial tension and 1.4% compression, respectively), and are suitable for enhanced-mobility field-effect transistor applications.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

新型负阻HBT构成的非稳多谐振荡器研究

报道了由超薄基区负阻异质结双极晶体管(UTBNDRHBT)构成的非稳多谐振荡器,具有高速、可调控等优点。对其电压控制脉冲频率调制效应进行了实验研究,观察到了仅由基极电压(V_(BE))即可控制脉冲间距和脉冲宽度;对实验现象给出了相应分析,并指出了此电路的应用前景。     

具有在片稳定网络的GaAs HBT微波功率管

采用GaAs标准MMIC工艺制作了具有片上RC并联稳定网络的InGaP/GaAs HBT微波功率管单胞.依据K稳定因子,RC网络使功率管在较宽的频带内具有绝对稳定特性.Load-pull测试表明RC网络没有严重影响功率管的大信号特性,在5.4GHz饱和输出功率为30dBm,在11GHz 1dB压缩点输出功率大于21.6dBm.功率合成电路验证了该功率管具有高稳定性,非常适合制作微波大功率HBT放大器.     

A novel SOI-MESFET with parallel oxide-metal layers for high voltage and radio frequency applications

In this paper a novel silicon on insulator metal-semiconductor field effect transistor is proposed for high voltage and radio frequency applications. This structure includes additional parallel oxide-metal layers in channel region which we called POML-SOI-MESFET. Our 2-D simulations demonstrate that the presence of parallel layers increases the breakdown voltage. Higher critical electric field of additional oxide region than Si and the effect of inserted metal layer in dispersing the potential lines at the gate edge and also at drift region, boost the breakdown voltage of the device from 13.5 V in conventional structure (C-SOI-MESFET) to 29 V in POML structure which shows 114% improvement. Maximum output power density experiences 133% enhancement by applying POML structure. Also, parallel layers improve the maximum oscillation and cut-off frequencies by 11% and 3.3%, respectively with modifying the gate-drain capacitance. Thermal analysis shows that beside these improvements, the POML maintains the thermal conductivity of the device. In order to attain the best results, POML dimensions are optimized carefully. Simultaneous improvement in breakdown voltage, cut-off frequency, maximum oscillation frequency, and maximum output power density makes our proposed structure an efficient device for applications with higher voltages and frequencies.