Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10¹⁷cm^-3, saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.     

Frequency limits of GaAs and InP field-effect transistors at 300 K and 77 K with typical active-layer doping

InP FET's with active layer doping of 10¹⁷donors/ cm³have limiting values of fTroughly fifty per cent higher than those of equivalent GaAs devices for lengths ranging from 0.5 µm to 3 µm at 300 K, and from eighty percent to forty percent higher in this gate length range at 77 K.     

Planar InP/InGaAsP three-dimensional graded-junction avalanche photodiode

A new planar InP/InGaAsP avalanche photodiode, which is fabricated by Be⁺implantation through a dish-shaped InGaAs mask, has been developed. A three-dimensional graded junction is obtained and a uniform gain as high as 30 achieved without edge or surface breakdown. The dish-shaped InGaAs implantation mask is formed by a photoelectrochemical etching technique. Device modeling indicates that the graded junction and low doping concentration can prevent edge breakdown and greatly suppress the surface field. The diode has a separated absorption and multiplication structure grown by hydride vapor-phase epitaxy. These devices exhibit low primary dark currents (≈ 1 nA), and high quantum efficiencies close to that of an InGaAs p-i-n at 1.3-µm wavelength. Sensitivity measurements at bit rates of 1.7 Gbit/s give a minimum average receiver power required for 10^-9BER of -35.5 dBm.     

A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.     

High performance epitaxial HgCdTe photodiodes for 2.7 µm applications

High performance photovoltaic devices tailored for 2.7 µm cut-off have been fabricated on liquid phase epitaxial HgCdTe/CdTe. The peak external quantum efficiency is measured to be 67% without any AR-coating. The measured zero-bias resistance-area (R0A) product is 5 ∼ 10⁴µ-cm²at 195K and µ10⁷Ω-cm²at 140K. The demonstrated performance of HgCdTe photovoltaic devices tailored for a 2.7 µm cut-off is considerably better than conventional PbS photodetectors, which have appeared in available literature and which are currently in wide use in this spectral range.     

Improved physics for simulating submicron bipolar devices

The conventional device physics in most numerical simulations of bipolar transistors may not predict the measured electrical performance of shallow heavily doped emitters and bases. This paper summarizes improved device physics for numerical simulations of solid-state devices with dopant densities up to about 3 × 10²⁰cm^-3and with junction depths as small as 0.1 µm. This improved device physics pertains to bandgap narrowing, effective intrinsic carrier concentrations, carrier mobilities, and lifetimes. When this improved physics is incorporated into device analysis codes such as SEDAN and then used to compute the electrical performance of n-p-n transistors, the predicted values agree very well with the measured values of the current-voltage characteristics and dc common emitter gains for devices with emitter-base junction depths between 10-0.16µm.     

Carrier distribution and low-field resistance in short n+-n--n+and n+-p--n+structures

In the present paper, we calculate the potential, field, and carrier distributions in short n⁺-n^--n⁺and n⁺-p^--n⁺devices and estimate the low-field resistance. The results of the calculations present a set of universal curves which may be used to find the minimum carrier density in the sample, the barrier height, the electric field at the boundary, etc. Our calculations show that electron injection becomes very important when the doping level is smaller than 1.5 × 10¹⁴(cm^-3). (T/300 K)/ L²(µm) for GaAs diodes, whereLis the sample length. The low-field resistance of the sample is limited by the thermionic emission of the sample and by the diffusion and drift in the sample. The thermionic emission dominates at low temperatures, in short samples, and the diffusion-drift dominates in longer samples at higher temperatures. The experimental values of low-field resistance for GaAs 0.4-µm n⁺-n^--n⁺devices at 77 and 300 K are in good agreement with the predicted values. The agreement is not so good for 0.25-µm devices and for n⁺-p^--n⁺devices. In the latter case, the disagreement may be due to uncertainty in the doping level because the low-field resistance of the n⁺-p^--n⁺structure is shown to be very sensitive to the doping level of the p-region.     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Geometrical factors in avalanche punchthrough erase

It is known that the surface potential of an IGFET can be raised to high levels by reverse-bias pulsing its source and drain. This high surface potential is contingent upon both punchthrough and avalanche injection of majority carriers into the surface region. Erase of some multilayer charge storage memory cells is accomplished using such an avalanche punchthrough erase (APTE) operation. In this paper the maximum surface potential achievable in this manner is assessed for a variety of geometries. The calculation is based upon a Fourier sine transform solution of Poisson's equation, coupled with the sampling theorem for spatially localized functions. The depletion width is determined self-consistently and is found to vary from a minimum value at mid-channel to a maximum value at the channel ends. It is found that the maximum surface potential is achieved for devices whose junction depth is comparable to or greater than the channel length. Under these conditions the surface potential can be as large as the reverse bias less the punchthrough voltage. To avoid serious short-channel behavior during normal read operations, it is suggested that the conditionNl^{2} > 2V_{D}kisin_{0}/ebe observed, whereN= doping level/cm³,l= half channel length, VD= drain voltage during read, K = dielectric constant of semiconductor, ∈0= permittivity of free space,e= electronic charge. Thus for a 2-µm channel length we recommend a junction depth ≥2 µm, and a doping level ≈6.5 × 10¹⁵/cm³for a memory cell which is to use APTE and a read voltageV_{D} simeq 5V.     

Silicon Oxide enhanced Schottky gate In0.53Ga0.47As FET's with a self-aligned recessed gate structure

We present the fabrication and characterization of an In0.53Ga0.47As enhanced Schottky gate FET with a self-aligned recessed gate structure. A thin layer of e-beam evaporated silicon oxide was used to reduce the gate leakage current. For a n-channel doping of 8 × 10¹⁶cm^-3and a gate length of 1.5 µm, these devices showed good pinchoff characteristics with transconductances of 150 mS/mm. The effective velocity of electrons at current saturation is deduced to be 2.4 × 10⁷cm/s at the drain end of the gate. At 3 GHz these devices have a maximum available gain of 10 dB, decreasing to 6 dB at 6 GHz.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Effect of exponentially graded base doping on the performance ofGaAs/AlGaAs heterojunction bipolar transistors

The authors have fabricated n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with base doping graded exponentially from 5×10¹⁹ cm^-3 at the emitter edge to 5×10¹⁸ cm^-3 at the collector edge. The built-in field due to the exponentially graded doping profile significantly reduces base transit time, despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping of 1×10¹⁹ cm^-3 , the cutoff frequency is increased from 22 to 31 GHz and maximum frequency of oscillation is increased from 40 to 58 GHz. Exponentially graded base doping also results ill consistently higher common-emitter current gain than uniform base doping, even though the Gummel number is twice as high and the base resistance is reduced by 40%     

Multi-element reachthrough avalanche photodiodes

Two approaches to making multi-element arrays of p⁺-π-p-n⁺reachthrough avalanche photodiodes are reported. In the first approach a single common avalanche region (p-layer) for all elements is used, with the segmentation between elements being on the p⁺layer. This approach has the advantage of having zero dead space between adjacent elements, but is difficult to fabricate, and has a very narrow range of operation in which it is neither noisy due to injection nor suffers from poor element-to-element isolation. In a second approach, the p⁺contact is common and separate avalanche regions are used. The problem for this case is the width of the dead space between adjacent elements which, because of field-fringing effects, is considerably wider than the actual physical distance between elements. A self-aligning technique is described for fabricating arrays by the second approach and the technique demonstrated with a 25-element linear array on 300-µm centers. The measured dead space is in the 60-80 µm range, depending on the gain. The array can be used at an average gain of 100 or more, has excellent element-to-element isolation, and NEP's below 2 × 10¹⁵W/Hz^1/2at 800-900 nm and below 10^-14W/ Hz^1/2over the whole spectral range from 400 to 1060 nm.     

Bistable switching in supercritical n+-n-n+GaAs transferred electron devices

Bistable switching in supercritically doped n⁺-n-n⁺GaAs transferred electron devices (TED's) is investigated experimentally and interpreted in computer simulations, for which details of the computer program are given. Three switching modes all leading to stable anode domains are discussed, namely: 1) cathode-triggered traveling domain; 2) cathode-triggered accumulation layer; 3) anode-triggered domain. Relative current drops up to 40 percent, and switching times down to 60 ps are obtained in low-duty-cycle pulsed experiments with threshold currents around 400 mA. Optimum device parameters are shown to be as follows: 1) doping in the 3-4 × 10¹⁵cm^-3range; 2) length around 6 µm; 3) doping gradients below 20 percent; 4) high-quality interfaces.     

Optical microprobe response of GaAs diodes

GaAs p-n junction photocurrent response is obtained from an optical microprobe with a dynamic range of at least three decades and a light-spot diameter of about 1.3 µm. The results are found to correlate well with the appropriate theoretical response which includes surface recombination and assumed infinite absorption coefficient. Minority-carrier diffusion lengths computed from the data are typically 3.5 and 0.7 µm for holes in n-type material doped 10¹⁷and 1.4×10¹⁸cm^-3and 1 µm for electrons in >10¹⁸cm^-3doped p-type material. Estimates of carrier lifetimes are made and the deviation of surface recombination velocity between devices is demonstrated.     

Limitations on injection efficiency in power devices

In this paper the mechanisms of bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, and carrier-carrier and carrier-lattice scattering are included in an exact one-dimensional model of a bipolar transistor. The transistor is used as a vehicle for studying the relative importance of each of these phenomena in determining emitter efficiency in devices with emitter junction depths of 1 µm to 8 µm. It is shown that bandgap narrowing is the dominant influence for devices with shallow emitters of 2 µm or less and that SRH recombination dominates for emitter depths greater than 4 µm. Calculations are also presented showing the effects of the emitter surface concentration and high-level injection on the current gain for devices with emitter junction depths of 1 µm to 8 µm. It is shown that there is an optimum surface concentration of 5 × 10¹⁹cm^-3for the 1-µm emitter depth but no optimum under 10²¹cm^-3for devices with emitter depths greater than 4 µm.     

A novel camel diode gate GaAs FET

A novel device utilizing the "camel diode" in place of a Schottky barrier gate has been demonstrated in GaAs grown by molecular beam epitaxy (MBE). The devices have a 7.5 µm channel length, 3 µm gate length, and a 280 µm gate width. The layers from which the devices are fabricated consist of a 0.15 µm GaAs layer doped to a level of 1.5 × 10¹⁷cm^-3to form the channel, and a 100 Å p+GaAs and a 400 Å n+ region to form the gate. Because of the long gate length, the electron velocity does not reach saturation, thus a transconductance of 80 mS/mm is obtained. A simple theory describing the device operation has also been developed.     

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 10²⁰/cm³have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.     

Junction field-effect transistors using In0.53Ga0.47As material grown by molecular beam epitaxy

In this article we discusss the fabrication of junction field-effect transistors (JFETs) using In0.53Ga0.47As grown p-n junction material prepared by molecular beam epitaxy (MBE). For an n-channel doping of 2 × 10¹⁶cm^-3and a gate length of 2.0µm, these devices are shown to have a transconductance of 50 mS/mm with a corresponding internal transconductance of 67 mS/mm.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.