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提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响. 相似文献
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提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响. 相似文献
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随着集成电路制造工艺进入超深亚微米阶段,漏电流功耗在微处理器总功耗中所占的比例越来越大,在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化漏流功耗成为业界研究的热点.Cache在微处理器中面积最大,是进行漏流控制的首要部件.LRU是组相联Cache最常用的替换算法,而研究发现,访存操作命中LRU后半区的概率很低.LRU-Assist算法以Drowsy Cache、Cache Decay等控制策略为基础,在保证处理器性能不受影响的前提下,利用既有的LRU信息把Cache的关闭率平均提高了15%,大大降低了漏电流功耗. 相似文献
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在集成电路静态老化测试中,对被测电路持续施加特殊的固定测试矢量,使被测电路产生较大的漏电功耗,有利于其早期失效的发生,获得更好地老化效果.提出一种产生最大漏电功耗的测试矢量选取方法.在被测电路中设置合适的固定故障,通过ATPG方法获取较小的备选测试矢量集合.基于门电路的故障相关输入状态,设计了一种度量指标,可用于辅助在备选测试矢量集合中搜索目标矢量.该度量指标与电路漏电功耗总体上为正相关关系,可有效降低误选测试矢量的风险. 相似文献
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FPGA已经被广泛用于实现大规模的数字电路和系统,随着CMOS工艺发展到深亚微米,芯片的静态功耗已成为关键挑战之一。文章首先对FPGA的结构和静态功耗在FPGA中的分布进行了介绍。接下来提出了晶体管的漏电流模型,并且重点对FPGA中漏电流单元亚阈值漏电流和栅漏电流进行了详细的分析。最后根据FPGA的特点采用双阈值电压晶体管,关键路径上的晶体管采用低阈值电压栅的晶体管,非关键路径上的晶体管采用高阈值电压栅的晶体管,以此来降低芯片的静态功耗。 相似文献
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一、漏电流的产生分类一般漏电流分为四种,分别为:半导体元件漏电流、电源漏电流、电容漏电流和滤波器漏电流1、半导体原件漏电流PN结在截止时流过的很微小的电流。D-S正向偏置,G-S反向偏置,导电沟道打开后,D到S才会有电流流过。但实际上由于自由电子的存在,自由电子的附着在SIO2和N+、导致D-S有漏电流。 相似文献
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对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述.以期为相关研究:设计人员提供有益参考。 相似文献
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The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach. 相似文献
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Makino H. Matsue S. Noda M. Tanino N. Takano S. Nishitani K. Kayano S. 《Solid-State Circuits, IEEE Journal of》1990,25(5):1232-1238
A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C 相似文献
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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(5):374-378
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Gupta S. K. Raychowdhury A. Roy K. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2010,98(2):160-190
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A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing. 相似文献
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Lin Yuan Gang Qu 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(2):173-182
Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively. 相似文献
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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits 总被引:11,自引:0,他引:11
Roy K. Mukhopadhyay S. Mahmoodi-Meimand H. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2003,91(2):305-327
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption. 相似文献
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Design and Analysis of Two Low-Power SRAM Cell Structures 总被引:2,自引:0,他引:2
Razavipour G. Afzali-Kusha A. Pedram M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(10):1551-1555
In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation. 相似文献
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A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively. 相似文献