A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

Turn-off processes in high-voltage n-p-ν-n switches

A one-dimensional solution is found for the current-continuity equations that govern minority-carrier removal from the collector region of a saturated bipolar transistor. The shape and position of the charge body is established so that the collector-voltage rise can be predicted, especially in the final stages of turn-off. Constant collector current, corresponding to an inductive load, is assumed during the charge-removal process. The effect of varying the reverse base drive is considered as is turning off from hard- and quasi-saturation. It is shown that the collector region can be swept clear of minority carriers at a collector voltage well below BVCEO. Once minority carriers have been cleared, collector current is supported by a displacement current which causes energy storage, rather than dissipation. Experimental verification is sought with a developmental transistor that minimizes two- and three-dimensional effects. Qualitative agreement is evident; reasonable quantitative agreement does not require unrealistic assumptions. Lastly, the conditions that can precipitate reverse-biased secondary breakdown are identified in an appendix.     

Distribution of recombination current in emitter-base junctions of silicon transistors

Sah, Noyce and Shockley have attributed the decrease in the current gain of silicon transistors to recombination in the space-charge region of the emitter-base junction. It is suggested that for oxide-masked diffused structures the space-charge recombination current is concentrated at the junction periphery at or just under the surface. An analysis is presented which shows that measurement of the base current of transistor structures with two base contacts, as a function of voltage applied between the two base contacts, may be used to distinguish between recombination current which is concentrated at or near the surface periphery of the junction space-charge region, and recombination current distributed over the area of the junction. For the diffused structures examined, it is shown experimentally that the recombination takes place mainly at or near the junction surface periphery.     

Inverse base-width modulation and collector space-charge-regionwidening: degrading effects at high current densities in highly scaledBJT's (and HBT's)

Degrading effects on BJT speed performance due to current-induced perturbation of the collector-base junction space-charge region (SCR) prior to base pushout are analyzed and assessed. Inverse base-width modulation (IBWM)-a widening of the quasi-neutral base width-and collector SCR-width widening (SCRW) in highly scaled BJT's and HBT's are identified as important mechanisms governing device speed degradation at high currents. IBWM, which increases the base transit time, is described analytically to distinguish it from base pushout, or quasi-saturation. MMSPICE simulations of an aggressive SiGe-base HBT technology, supported by measured data, show that the speed (f_T) degradation associated with IBWM is significant at currents well below the onset of base pushout, which underlies the speed degradation of lesser scaled BJT's. Simulations of further scaled devices show that SCRW can be the predominant mechanism of speed degradation at high current densities     

Noise in solid-state devices and lasers

A survey is given of the most important noise problems in solid-state devices. Section II discusses shot noise in metal-semiconductor diodes, p-n junctions, and transistors at low injection; noise due to recombination and generation in the junction space-charge region; high-level injection effects; noise in photodiodes, avalanche diodes, and diode particle detectors, and shot noise in the leakage currents in field-effect transistors (FETs). Section III discusses thermal noise and induced gate noise in FETs; generation-recombination noise in FETs and transistors at low temperatures; noise due to recombination centers in the space-charge region(s) of FETs, and noise in space-charge-limited solid-state diodes. Section IV attempts to give a unified account of 1/f noise in solid-state devices in terms of the fluctuating occupancy of traps in the surface oxide; discusses the kinetics of these traps; applies this to flicker noise in junction diodes, transistors, and FETs, and briefly discusses flicker noise in Gunn diodes and burst noise in junction diodes and transistors. Section V discusses shot noise in the light emission of luminescent diodes and lasers, and noise in optical heterodyning. Section VI discusses circuit applications. It deals with the noise figure of negative conductance amplifiers (tunnel diodes and parametric amplifiers), and of FET, transistor, and mixer circuits. In the latter discussion capacitive up-converters, and diode, FET, and transistor mixers are dealt with.     

Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. Tlris leads to the formation of p/sup +/ -n/sup +/ junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p/sup +/-n/sup +/ junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Avalanche-induced 1/f noise in bipolar transistors

It has been proposed that degradation of low current hFE, as a result of avalanching the emitter-base junction of a bipolar transistor, can be attributed to an increase in surface recombination velocity within the emitter-base space-charge region. This work shows that 1/fnoise is also increased during avalanche and that this increase is consistent with a previously reported correlation between surface recombination velocity and 1/fnoise.     

Functional modeling of integrated injection logic—Transient analysis

A transient analysis of integrated-injection logic I²L structures is presented. This analysis is based on calculating the different depletion and neutral region charges. Doping profile, high-level effects, and geometrical layout are taken into account. To formulate a transient functional model of the structure, regional transient delays are defined as ratios of the corresponding charges to the electron current density Jnof the n-p-n vertical transistor. An analytical expression is given for the dominant storage time; τepi. The ratio of the stored charges in a metal-covered and oxide-covered base region is related to the surface recombination velocity and the ratio of the corresponding current densities. In a partitioned CAD model (as in Berger's injection model), the regional transient delays are expressed in terms of the corresponding current densities rather than Jn. The computed results for a five-state ring oscillator are compared to measurements.     

Emitter injection efficiency in heterojunction bipolar transistors

Experimental approaches for measurement of the emitter injection efficiency in heterojunction bipolar transistors are discussed. The electron and hole currents crossing the base-emitter junction and the currents recombining within the quasi-neutral emitter and base region are also determined. The influence of the interface and space-charge region recombination is discussed qualitatively. New figures of merit for a bipolar transistor are introduced. Preliminary experimental results obtained on AlGaAs/GaAs transistors are presented.     

A theory of transistor cutoff frequency (fT) falloff at high current densities

It is shown that the observed falloff in the fTof a transistor at high currents is due to the spreading of the neutral base layer into the collector region of the device at high current densities. The base layer spreading mechanism derives from an analysis of the effect of the current-dependent buildup of the mobile-carrier space-charge density in the collector transition layer. Calculations show that at sufficiently high collector current levels, the mobile space-charge density in the collector transition layer cannot be considered negligible in comparison to the fixed charge density of that region. The over-all effect of taking the mobile space charge into account in analyzing the collector transition region is that, at high current densities, the transition region boundary adjacent to the neutral base layer is displaced toward the collector metal contact with increasing collector current. The attendant widening of the neutral base layer results in the observed, high-current falloff in fT. The application of this theory to transistor structures of both the alloy and mesa variety yields, in each case, calculated curves of fTvs Icwhich are in reasonably good agreement with experiment.     

Simulation study of high injection effects and parasitic barrier formation in SiGe HBTs operating at high current densities

The effects of high carrier densities near the base–collector (B–C) heterojunction in npn SiGe heterojunction bipolar transistors during device operation at high current densities has been investigated using a commercial numerical device simulator. Due to electron velocity saturation in the B–C space charge region and the presence of the valence band discontinuity at the B–C junction, hole accumulation occurs at the collector end of the base at the onset of base pushout at high current densities. Formation of a parasitic barrier to electron flow in the conduction band occurs at the collector junction which increases recombination in the base and the base current and produces saturation in the collector current. Together, these effects produce an abrupt degradation in the transistor’s current gain and cutoff frequency with increasing emitter junction bias. In this paper, we investigate the onset and relationship of parasitic barrier formation and base pushout, and their dependence on device structure and biasing.     

Switching response of graded-base PN junction diodes

This paper extends the earlier analysis by Kingston of the switching response of a uniform-base diode to a graded-base diode. It concerns the time required to switch a diode from a forward-biased to a reverse-biased condition. The current transient can be separated into two phases: 1) the constant current phase during which the carrier density at the junction changes gradually from a forward-biased to a reverse-biased condition, and 2) the nonconstant current phase during which the injected carriers stored in the base region gradually disappear. In the present analysis, it is found that in a graded-base diode where the impurity concentration decreases from the emitter junction towards the base contact, the time for the constant current phase is greatly shortened because of favorable initial carrier distribution. The effect is already significant if the impurity concentration changes by a factor from 3 to 1 from the emitter junction to the base contact. To shorten the nonconstant current phase, however, a much larger change of impurity concentration, say of the order from 500 to 1, from the emitter junction to the base contact is needed.     

Simplified computer-aided analysis of double-diffused transistors including two-dimensional high-level effects

An approximate two-dimensional numerical analysis has been developed for studying double- (or triple-) diffused transistors. The program supplies dc and hf terminal characteristics (e.g., hfe, rbb, fT, IB, VBE) over a wide range of operating collector currents and voltages for a given set of physical device parameters (mask dimensions, impurity profile, etc.). The approach is based on obtaining a set of differential equations describing current flow in the longitudinal (emitter-collector) direction and a separate differential equation describing current flow in the lateral direction. The assumption is made of space-charge or space-charge-neutral regions with current- and voltage-dependent boundaries. The equations are valid for arbitrary injection levels and automatically include such high-level effects as conductivity modulation, base widening, and emitter current crowding. Both theoretical and experimental results are given for transistors with fTvalues between 100 MHz and 3 GHz. The validity of the approach is confirmed and some areas requiring further study are outlined. The technique described is felt to be particularly attractive for the design and optimization of high-power microwave devices, due to the small computer execution time and memory requirements.     

Analysis of the operation of GaAlAs/GaAs HBTs

Drift-diffusion modeling in two dimensions has been used to characterize and analyze storage, transport and recombination effects in GaAlAs/GaAs heterostructure bipolar transistors. Both intrinsic and parasitic effects have been studied, and their relationship to the design of the device is discussed. For conventional dopings and high current densities, the heterojunction grading potential causes a barrier in the base-emitter junction, which results in a large increase in the dynamic resistance. In heterojunction collectors, a similar barrier leads to a large increase in base charge storage and to spreading of the collector current. It is shown that increased doping levels can successfully suppress these barrier effects. The capacitance and transport phenomena at the base-emitter junction are also analyzed under conditions of large forward bias, where the junction space-charge region is shorter than the alloy grading length. Recombination is analyzed in the limit of high surface recombination velocities using Shockley-Read-Hall theory in the presence of Fermi-level pinning due to surface states. The pinning results in a potential energy saddle point at the edge of the base-emitter junction, which largely determines the surface recombination behavior of the transistor when the recombination velocity is high     

Evaluation of the DC parameters and noise transport in the gun region of an injected-beam crossed-field diode

A half-Maxwelliany-component velocity distribution and a full-Maxwellianz-component velocity distribution are assumed in order to evaluate the position and depth, ymand Vm, of the potential minimum as a boundary-value problem. The various dc parameters such as the voltage distribution, space-charge density, velocity and current density components and trajectories are then evaluated as an initial-value problem. The results obtained in this manner agree closely with the results obtained from the Kino gun model except that they-component current density is not constant, as is usually assumed in the Kino gun model. The steady-state parameters are calculated here for both temperature-limited and space-charge-llmited conditions. The Kino gun results are shown to be essentially those for space-charge-limited operation. Even though the injection conditions under the two types of operation are identical, the formation of a potential minimum considerably changes the electron trajectories and the corresponding velocity components. The growth rate of a hybrid wave is reduced as ωpis decreased and/oromega/omega_{c}is increased, and the propagation constants of the two conventional space-charge waves are modified, the over-all growth rate of the slow wave being greater than that of the fast wave. For large values of ωpthe conventional fast space-charge wave is a backward wave, although it becomes a forward wave ifomega/omega_{c}is large. It is noticed that the conditions in the gun region are more favorable to the existence of low-frequency perturbations. Based upon these results several experimental observations made at various laboratories are explained qualitatively.     

A physical theory of junction transistors in the collector-voltage-saturation region

A physical theory has been formulated for the operation of junction transistors in the "collector-voltage-saturation" region or "on" region. Transistor characteristics in this region are important for switching applications, Class A or Class B amplifiers, as well as other large signal applications. The formulation is based on the physical consideration that in the "collector-voltage-saturation" region the collector-base junction is forwardly biased, and that the injection level is high. Two-dimensional distributions of carrier densities, current densities, and electric field are obtained for separate portions of the base region. Using these distributions, theoretical expressions are derived for the characteristics of p-n-p and n-p-n transistors including saturation voltage, base input voltage, and dc current amplification factor. Good agreement between theoretical and experimental results indicates that the approximations used in the theory are valid. Numerical calculations have been carried out for the saturation voltage, base input voltage, and dc current amplification factor for different geometrics and material properties. The calculation illustrates the use of the theory for quantitative designs of transistor characteristics.     

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.     

Space-charge layer width in diffused junctions

This paper outlines a calculation of space-charge layer width in a planar junction made by diffusing an n or p impurity (assumed to follow a Gaussian or a complementary error function distribution) into a uniformly doped crystal of opposite conductivity type. The collector junction of most drift transistors conforms closely to this model. An exponential approximation to the impurity distribution permits curves to be drawn of the space-charge layer penetration in each direction from the junction as a function of applied reverse voltage, and of the electric field distribution. The quantities involved are normalized in terms of the initial doping level N1, the impurity diffusion lengthL = 2 sqrt{Dt}, and the junction depth xj. The curves should be useful in calculating depletion-layer capacitance, transistor punch-through voltage and junction breakdown voltage.     

Applications of junction compensation techniques in reducing transient gamma radiation effects in transistor circuits

Any transistor exposed to transient gamma radiation will produce a large transient photocurrent output pulse unless the circuit is hardened or protected against this effect. The hardening technique described in this paper consists of adding a reverse-biased junction between the collector and the base of a transistor, producing a photocurrent which cancels or compensates for the radiation-induced current. Both computer and experimental results show a significant hardening achieved by this method which is applicable to microcircuit systems as well as to discrete component systems.