GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

A new, precharged, low-power logic family for GaAs circuits

We present a new precharged, low-power logic family in GaAs that operates at speeds comparable to DCFL and consumes about one-fourth the power of DCFL. It uses a 2 V power supply for operation and can be used in conjunction with the widely used DCFL circuits. The logic family allows us to build complex gates in one gate delay, provides better noise margins, and is less susceptible to load capacitances than an unbuffered DCFL gate, thus making it useful for standard-cell based designs. To verify the approach, we have designed and fabricated a fully functional test chip containing a precharged full adder     

Dynamic latch for high speed GaAs domino circuits

A latch for use with GaAs domino logic gates is presented. A hybrid of a GaAs domino logic gate and a two-phase dynamic FET logic gate, the latch stores data during the precharge phase of domino logic operation. It enables the use of domino logic in large scale systems without the need for interfacing with power consumptive static latches. It is implemented with depletion mode MESFETs and dissipates 0.8 mW.<>     

Pseudo-complementary FET logic (PCFL): a low-power logic family inGaAs

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET's only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 μm MESFET process. The power consumption of an inverter is about 10 μW at 100 MHz     

GaAs MESFET differential pass-transistor logic

Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms     

GaAs pseudodynamic latched logic for high performance processorcores

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems     

Design and performance of multistage GaAs dynamic logic

GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation     

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.     

GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

Gallium arsenide finds a new niche

The use of a very-large-scale integrated GaAs circuits for applications where high speed at room temperatures is needed, such as in computers or telecommunications, is examined. The advantages and disadvantages of a logic family called direct-coupled FET logic (DCFL) which couples the speed of GaAs with a significantly lower power dissipation than any other alternative are discussed. Material, fabrication, and packaging concerns associated with DCFL are considered. Some GaAs devices being produced in volume, at rates of several hundred a month, are described. The potential impact of these devices on the computer and telecommunications markets is addressed     

PCFL3: a low-power, high-speed, single-ended logic family

This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%     

简易逻辑分析仪设计

本系统是以STC89C52单片机和复杂可编程逻辑器件CPLD的组合电路为核心,利用锁存器在时钟上升沿将输入端的数据锁存的原理,构建了一个基于实时采样和直接数据存储器存储（DMA）的简易逻辑分析仪。系统由五部分组成：按键模块、CPLD模块、DDS采样时钟发生模块、LCD显示模块、DMA数据采集模块。相比于市场上的逻辑分析仪,本系统结构简单,易制作,成本低,可同时测量8路TTL信号。本系统可以用来分析数字逻辑电路中的时序逻辑关系,本文还用该逻辑分析仪研究了51单片机对外部地址读写操作的时序,得到与单片机数据手册一致的波形时序图。     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

Advantages of metallic-amorphous-Silicon-gate FET's in GaAs LSI applications

A Schottky barrier as high as 1 V is obtained for contact between a ternary amorphous film, a-Si-Ge-B, and an n-type GaAs crystal. A metallic-amorphous-silicon-gate FET (MASFET) was made using the amorphous film as a gate contact. GaAs MASFET characteristics are superior to GaAs MESFET characteristics in application to LSI's with a DCFL configuration because the DCFL circuits with the GaAs MASFET's provide a logic level as high as 0.94 V and widen the circuit operation margin. Full operation is obtained from a 1 Kword × 2 bit SRAM with GaAs MASFET's, which is considered to be mainly due to the wide operation margin. The measured propagation delay time of the DCFL inverter is 34 ps at supply voltageV_{DD} = 1.5V and power consumption of 1.9 mW/gate.     

一种单锁存器CMOS三值D型边沿触发器设计

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计.该电路是通过时钟信号的上升沿后产生的窄脉冲使锁存器瞬时导通完成取样求值.所提出的电路较之以往设计具有更为简单的结构,三值双轨输出时仅需24个MOS管.计算机模拟结果验证了所提出的触发器具有正确的逻辑功能、良好的瞬态特性和更低的功耗.此外,该设计结构极易推广至基值更高的多值边沿触发器的设计.     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX     

Pass-transistor adiabatic logic with NMOS pull-down configuration

A new low power adiabatic logic family, pass-transistor adiabatic logic with NMOS pull-down configuration, is presented. For a 2:1 multiplexer, a power saving of ~800% is achieved, compared to a 2N-2N2P logic circuit at 20 MHz. Compared to pass-transistor adiabatic logic using single power-clock supply (PAL), the `tri-state' problem is solved, while power consumption is comparable. A four phase sinusoidal clock power supply is employed in the new logic family, which facilitates pipelining hence leading to higher throughput, compared to PAL     

Gallium arsenide pseudo-dynamic latched logic

A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems