Nonvolatile static read/write memory cell using CMNOS structure

A new type of nonvolatile static read/write memory cell constructed with three MOS transistors and one MNOS transistor is proposed. The MNOS transistor and one of the MOS transistors involved are complementary combined to offer binary states in the Λ-shapedI-Vcurve for memory operation under normal power supply. Upon power failure, the MNOS transistor acts as a back-up element for nonvolatility. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.     

New two-terminal C-MNOS memory cells

New two-terminal nonvolatile memory cells are proposed, in which an n-channel MNOS transistor is functionally integrated with a p-channel MNOS or MOS transistor. The operational principle of both types of the cells is substantially based on the Λ (lambda)-shaped I-V Characteristic of complementary FET's. The most valuable feature of the new cells is the unipolar pulse operation of the simple diode-matrix array which can be used in a RAM mode by the use of selective writing and erasing as well as in an electrically alterable PROM mode.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Silicon-gate CMOS frequency divider for electronic wrist watch

An integrated complementary MOS transistor scale-of-two counter for applications in electronic wrist watches has been realized. Silicon-gate technology applied to a very simple but safe dividing circuit has resulted in a substantial reduction of the total area of the integrated structure with the following performance. At a supply voltage of 1.35 V the maximum frequency is 2 MHz and the dynamic power consumption per stage is 1.6 nW/kHz. The complementary substrate is obtained by a sealed-capsule low-surface concentration diffusion and doped oxides as impurity sources are used to allow simultaneous diffusion of both types of MOS transistors. A simple dynamic circuit derived from the basic structure is described.     

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.     

MOS晶体管技术

简要回顾MOS晶体管一些具有代表性的技术进展,分析了其在将来超大规模集成电路(ULSI)应用中的主要限制.从材料以及器件结构两个方向分别阐述了突破现有MOS技术而最有希望被将来ULSI工业所采用的新型晶体管技术.     

A novel two-dimensional MOS transistor for analog applications

In analog MOS integrated circuits, matching between transistors is a critical requirement because the circuit performance is determined by the device matching available. A new type of matched configuration is presented in this paper which utilizes the inherent 2-D geometry of an MOS transistor which was hitherto unexplored. This has been achieved by adding two more diffusion regions along the length of a normal MOS transistor. The characteristics of the device thus formed have been modeled in the linear region for different configurations, by solving the 2-D current continuity equation. For the saturation region, an empirical relation has been given. Theoretical and experimental results for a test chip have been presented. A few potential applications are mentioned.     

A Complementary Pair of Four-Terminal Silicon Synapses

We have developed a complementary pair of pFETand nFET floating-gate silicon MOS transistors foranalog learning applications. The memory storage is nonvolatile;hot-electron injection and electron tunneling permit bidirectionalmemory updates. Because these updates depend on both the storedmemory value and the transistor terminal voltages, the synapsescan implement a learning function. We have derived a memory-updaterule for both devices, and have shown that the synapse learningfollows a simple power law. Unlike conventional EEPROMs, thesynapses allow simultaneous memory reading and writing. Synapsetransistor arrays can therefore compute both the array output,and local memory updates, in parallel. We have fabricated prototypesynaptic arrays; because the tunneling and injection processesare exponential in the transistor terminal voltages, the writeand erase isolation between array synapses is better than 0.01 percentThe synapses are small, and typically are operated at subthresholdcurrent levels; they will permit the development of dense, low-powersilicon learning systems.     

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.     

MNOS/CCD nonvolatile analog memory

MNOS storage sites have been integrated with an n-channel CCD to produce a nonvolatile memory capable of storing sampled analog signals. Analog signals, sampled at the CCD input, are stored as trapped charge in the MNOS dielectric and may be replicated nondestructively after four days of storage with a linear dynamic range of 33 dB.     

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f ^a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.     

Negative-resistance MOS transistor

The author proposes a novel approach for implementing a negative-resistance MOSFET that uses a non-uniform drain-current flow within one integrated structure. This MOS device exhibits a negative output conductance within a specific bias range as a consequence of current sharing between two MOSFETs of different geometries. The author describes a negative-resistance MOS transistor and discusses in detail its principle of operation, design, and electrical characteristics. The MOSFET is a three-terminal voltage-controlled device that consists of two MOS transistors with the same type of channel conductivities and can be implemented either in n-channel or p-channel versions. The proposed device is a compact element that can be fabricated together with other semiconductor devices using a standard CMOS technology     

Design optimization of JCMOS structures

JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure.     

E2FAMOS—An electrically eraseable reprogrammable charge storage device

A new electrically eraseable nonvolatile charge storage device is described. The electrically eraseable floating-gate avalanche injection MOS (E²FAMOS) structure is an n-channel dual-stacked-gate MOS transistor programmed by avalanche injection from the pinchoff region and erased by hot electron injection from the floating gate.     

Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

An input-free V extractor circuit using a series connection of three transistors

This paper describes a self-biased MOS transistor circuit with the ground referenced output voltage equal to the threshold voltage V _T. The circuit employs a series connection of three transistors where the middle transistor is in linear operation and external transistors are in saturation. The circuit can be applied for V _T extraction of both n-channel and p-channel transistors. The range of currents for better measuring of V _T in each case is established by simulation.     

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

Low-voltage linear transconductor and a memory current using the MIFGMOS Transistor

The aim of this article is to probe the advantages that the Multi-Input Floating Gate MOS (MIFGMOS) transistor has versus the conventional MOSFET transistor in order to design analogue circuits with low-voltage operation and good linearity. To show this, the design and implementation of both a voltage to current converter (VIC) cell and a memory current cell (MIC) using MIFGMOS transistors is presented. The development is based on mathematical and simulation analysis as well as experimental results. Both cells present good performance and linearity according to theoretical analysis with a supply voltage of 1.7 V and a power consumption of about 20 μW, despite the long channel technology. These characteristics could be very important in analogue and mixed signal applications requiring low supply voltage and low power consumption. The cells presented here can be part of a sample and hold circuit operating in current mode, but applications are not restricted. Additionally, a comparison between simulation and experimental results obtained when we tested five 3-input MIFGMOS transistors are included to show their properties and behavior.     

Charge-based chemical sensors: a neuromorphic approach with chemoreceptive neuron MOS (C/spl nu/MOS) transistors

A novel chemoreceptive neuron MOS (C/spl nu/MOS) transistor with an extended floating-gate structure has been designed with several individual features that significantly facilitate system integration of chemical sensing. We have fabricated C/spl nu/MOS transistors with generic molecular receptive areas and have characterized them with various fluids. We use an insulating polymer layer to provide physical and electrical isolation for sample fluid delivery. Experimental results from these devices have demonstrated both high sensitivity via current differentiation and large dynamic range from threshold voltage shifts in sensing both polar and electrolytic liquids. We have established electrochemical models for both steady-state and transient analyses. Our preliminary measurement results have confirmed the basic design and operations of these devices, which show potential for developing silicon olfactory and gustatory units that are fully compatible with current CMOS technology.     

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in strong inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.