300 mm Conversion challenge and breakthrough for future semiconductor manufacturing

The status regarding the planned conversion of the semiconductor industry to the larger and more productive 300 mm wafer size is reviewed. Many efforts are already underway to aid the conversion to 300 mm wafers. In addition to the consortiums in both U.S. and Japan, targeted at working with the equipment manufacturers and standard setting, SEMICONDUCTOR300, a joint venture between Motorola and Siemens, will develop a fully integrated process (64M/256M) on a complete toolset. Goal of the SC300 operation is to realize and demonstrate concepts to reduce the cost/die on 300 mm in comparison to 200 mm of approx. 30–40%. A financial model for semiconductor manufacturing using the larger substrates is offered along with the productivity opportunities for each of the equipment types. The authors define equipment manufacturers in terms of performance and financial targets. Achieving these targets is critical to making the conversion happen as well as determining the timing. Finally, the authors offer the breakthrough technologies expected to occur at the 300 mm production level. The noticeable difference between the 300 mm generation of wafer processing in comparison to previous 150 mm and 200 mm conversions is the increase in automation requirements. The 300 mm wafer size will change the way semiconductor factories operate. This presentation offers thoughts of what changes will be required to facilitate 300 mm wafers and beyond.     

Three hundred-mm wafers: a technological and an economical challenge

For the transition from 200- to 300-mm wafers, in addition to the technological challenges, there is the equivalent cost challenge to be met. The ultimate target is cost parity per unit area of silicon between 200 and 300 mm. The major blocking point to be cleared appears to be crystal pulling. The question of cost of crystal pulling is mainly related to the large crystal weights (>300 kg) and to the issue of crystal defects (crystal originated pits (COPs); voids in the Si crystal) generated by crystal pulling. An alternative route to address the defect problem is to use epitaxy to create a defect-free layer of Si for the active device regions. Close co-operation between wafer manufacturers and users is absolutely necessary to address these key issues. Furthermore, to contain cost, wafer makers and device manufacturers have to work together intensively to implement standardisation wherever possible and to avoid cost driving overspecifications (e.g. for front and backside particles or flatness).     

Reliability assessment from fatigue micro-crack data

Micro-cracks are generally defined to be cracks less than 1 mm in length, which propagate under cyclic stresses until they grow large and cause failure in an item (e.g. component or structure). This paper proposes a method of using data on `fatigue micro-crack growth in a material' to predict its reliability. It is increasingly important to model such cracks effectively, Their growth properties, which differ in several respects from larger cracks, are discussed. The paper develops a hierarchical model for the propagation of micro-cracks in a material. This stochastic model attempts to model the dependence of growth on local conditions, varying throughout the material, that causes variation in growth rates across the specimen. Given the model, data on micro-crack growth are used to compute posterior distributions of model parameters, from which a predictive distribution for reliability can be calculated. Computation of the posterior distributions is by Gibb's sampling and kernel density estimation. The methodology is illustrated with two data sets, one simulated and the other from a cast-iron specimen. Some possibilities for further work are presented     

Defect requirements for advanced 300 mm DRAM substrates

In the background of increasing requirements for advanced 300 mm DRAM substrates, the possibilities of balancing defect requirements versus cost and feasibility are discussed. For DRAMs based on deep trench capacitors, the main focus regarding defects is on voids, so-called crystal originated pits (COPs), which are present in the commonly used vacancy rich silicon crystals. Whereas for the material used for recent DRAM design rules, the typical COP sizes around 150 nm have still been sufficiently small not to deteriorate the yield of the DRAM products, for future design rules a reduction of COPs in the device active area will be required. Since the conversion to 300 mm wafers is purely cost driven, a solution has to be found for making 300 mm low defect wafers cost effective for the usage even on products under a high cost pressure like DRAM.A promising material option is 300 mm high temperature annealed wafers, which are on the one hand able to fulfil the future requirements in terms of performance and offer on the other hand also the potential to become a cost effective substrate by implementation of cost saving opportunities. The task of the wafer users is to critically review the requirements and to identify essential needs in contrast to “nice to have” items. For 300 mm annealed wafers, the requirements regarding COP reduction and slip performance are discussed.     

Cost-effective traffic grooming in WDM rings

We provide network designs for optical add-drop wavelength-division-multiplexed (OADM) rings that minimize overall network cost, rather than just the number of wavelengths needed. The network cost includes the cost of the transceivers required at the nodes as well as the number of wavelengths. The transceiver cost includes the cost of terminating equipment as well as higher-layer electronic processing equipment, which in practice can dominate over the cost of the number of wavelengths in the network. The networks support dynamic (i.e., time-varying) traffic streams that are at lower rates (e.g., OC-3, 155 Mb/s) than the lightpath capacities (e.g., OC-48, 2.5 Gb/s). A simple OADM ring is the point-to-point ring, where traffic is transported on WDM links optically, but switched through nodes electronically. Although the network is efficient in using link bandwidth, it has high electronic and opto-electronic processing costs. Two OADM ring networks are given that have similar performance but are less expensive. Two other OADM ring networks are considered that are nonblocking, where one has a wide-sense nonblocking property and the other has a rearrangeably nonblocking property. All the networks are compared using the cost criteria of number of wavelengths and number of transceivers     

Uniform 3D hydrothermally deposited zinc oxide nanorods with high haze ratio

We present low cost hydrothermally deposited uniform zinc oxide (ZnO) nanorods with high haze ratios for the a-Si thin film solar cells. The problem of low transmittance and conductivity of hydrothermally deposited ZnO nanorods was overcome by using RF magnetron sputtered aluminum doped zinc oxide (ZnO:Al ~300 nm) films as a seed layer. The length and diameters of the ZnO nanorods were controlled by varying growth times from 1 to 4 h. The length of the ZnO nanorods was varied from 1 to 1.5 µm, while the diameter was kept larger than 300 nm to obtain various aspect ratios. The uniform ZnO nanorods showed higher transmittance (~89.07%) and haze ratio in the visible wavelength region. We also observed that the large diameters (>300 nm) and average aspect ratio (3–4) of ZnO nanorods favored the light scattering in the longer wavelength region. Therefore, we proposed uniformly deposited ZnO nanorods with high haze ratio for the future low cost and large area amorphous silicon thin film solar cells.     

湿法刻蚀应对圆片减薄后翘曲问题的探讨

随着微电子产业的发展,圆片直径越来越大、厚度越来越薄。一些本来不被关注的问题逐渐凸现出来。当150mm、200mm甚至300mm的圆片被减薄到200μm或者200μm以下时,圆片本身的刚性将慢慢变得不足以使其保持原来平整的状态。文章从圆片减薄后产生翘曲的直观表象入手,分析了产生翘曲问题的根本原因,采用湿法刻蚀的方式去除了圆片因减薄形成的背面损伤层,改善了圆片减薄后的翘曲问题。     

An on-line, business-oriented optimization of performance and availability for utility computing

Utility computing provides a pay-as-you-go approach to information systems in which application providers (e.g., web sites) can better manage their costs by adding capacity in response to increased demands and shedding capacity when it is no longer needed. This paper addresses application providers who use clusters of servers. Our work develops a framework to determine the number of servers that minimizes the sum of quality-of-service (QoS) costs resulting from service level penalties and server holding costs for the server cluster. The server characteristics considered are service rate, failure rates, repair rates, and costs. The contributions of this paper are: 1) a model for the performance and availability of an e-Commerce system that is consistent with data from a multisystem testbed with an e-Commerce workload; 2) a business-oriented cost model for resource allocation for application providers; 3) a closed form approximation for the optimal allocation of servers for an application provider based on the performance model in 1) and the cost model in 2); and 4) a simple criteria for utility owners and server manufacturers to make tradeoffs between server characteristics.     

Robotic platform for human gait analysis

A hydraulically actuated platform with 4-degrees of freedom (4-DOF) was designed to be able to apply velocity- or acceleration-controlled floor surface perturbations to freely walking human subjects. The apparatus was required to provide velocity-controlled translational perturbations over the floor surface, rotational perturbations about the ankle joint, and acceleration-controlled vertical translational perturbations. The apparatus was physically constructed, and tested by both measurements of dynamics and repeatability. Crossover of movement from one DOF to another was shown to be less than 1 mm or 0.5 degrees for all desired perturbations. Repeated perturbations were nearly identical with a standard deviation of less than 0.2 mm over translational axes. The application of the platform to human gait research was demonstrated with a protocol of midstance phase perturbations (n=8). For this, the platform controller was programmed to randomly select one out of three conditions: (1) no movement (control); (2) upward perturbation of 0.8 g, 50 mm, 300 ms after heel contact; (3) downward perturbation of 0.8 g, 50 mm, 300 ms after heel contact. In total, 90 trials (3 conditions x 30 repetitions) were recorded for each subject. By singling out the SOL EMG and normalizing and averaging over the subject population, it was shown that the upward and downward perturbations elicited at least two distinctive stereotypical reflex responses in the ankle extensors, opposite in sign. All subjects reported comfort with the apparatus and nobody fell.     

A simple approximation to the renewal function [reliability theory]

The authors present a simple, easy-to-understand approximation to the renewal function that is easy to implement on a personal computer. The key idea is that, for small values of time, the renewal function is almost equal to the cumulative distribution function of the interrenewal time, whereas for larger values of time an asymptotic expansion depending only on the first and second moment of the interrenewal time can be used. The relative error is typically smaller than a few percent for Weibull interrenewal times. The simple approximation methods works very well with one term if not too much accuracy is required (e.g. in the block replacement problem) or if the interrenewal (failure) distribution is not exactly known (e.g. only the first two moments are known). Although the accuracy of the simple approximation can be improved by increasing the number of terms, this strategy is not advocated since speed and simplicity are lost. If high accuracy is required, it is better to use another approximating method (e.g. power series expansion or cubic splines method)     

On the Potential of SiGe HBTs for Extreme Environment Electronics

"Extreme environments" represents an important niche market for electronics and spans the operation of electronic components in surroundings lying outside the domain of conventional commercial, or even military, specifications. Such extreme environments would include, for instance, operation to very low temperatures (e.g., to 77 K or even 4.2 K), operation at very high temperatures (e.g., to 200/spl deg/C or even 300/spl deg/C), and operation in a radiation-rich environment (e.g., space). We argue that the unique bandgap-engineered features of silicon-germanium heterojunction bipolar transistors offer great potential to simultaneously satisfy all three extreme environment applications, potentially with little or no process modification, ultimately providing compelling cost advantages at the IC and system level.     

QoS-driven multicast routing in sparse-splitting optical networks

This paper investigates the quality-of-service (QoS)-driven multicast routing problem in a sparse-splitting optical network. The main objective is to minimize the total cost of wavelength channels utilized by the light-tree while satisfying required QoS parameters. In this paper, both the optical-layer constraints (e.g., optical signal power) and application-layer requirements (e.g., end-to-end delay and inter-destination delay variation) are considered as the QoS parameters. First, integer linear programming (ILP) formulations to solve the optimal multicast routing problem with the given QoS parameters are presented. Solving the ILP formulations for large-scale networks can easily overwhelm the capabilities of state-of-the-art computing facilities, and hence, a heuristic algorithm is proposed to construct a feasible light-tree that satisfies the required QoS parameters in large-scale networks. Simulation results demonstrate the performance of the proposed heuristic algorithm in terms of the cost of utilized wavelength channels.     

Multicarrier modulation for narrowband PCS

Investigation of multicarrier modulation has demonstrated the feasibility of using this modulation format to deliver relatively high channel bit rates (24 kbps) to a low cost, pager-like personal communications service (PCS) terminal that enjoys long battery life (e.g., one month on a few pen-light cells). This is to be compared to the 1200 bps carried by typical current paging systems or the 6250 bps attained by the new ERMES paging system. While more complex modulation formats, such as PSK and QAM, might achieve higher bit rates in less (power, size, cost) constrained environments, amplitude keying of the component subcarriers allows simple noncoherent energy detection that is found to be robust in this short message delivery application     

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

Macro- and microsegregation of Zn in bridgman-grown CdZnTe

One of the remaining problems in the use of CdZnTe material as substrates in liquid phase epitaxy (LPE) of Cd_xHg_1-xTe (CMT) layers is that of variation in lattice matching, i.e. Zn content, across substrates. This wil become increasingly important in the future as larger focal plane arrays of infrared detectors are required. The basic Bridgman growth process for CdTe/Cd_0.96Zn_0.04Te has been extended by applying the accelerated crucible rotation technique (ACRT). A marked reduction in axial Zn segregtion is seen in 50 mm diameter ACRT material, but this effect is smaller in the case of 75 mm diameter crystals. Radial variations in Zn content are small in both sizes of crystal, demonstrating the benefits obtained from ACRT stirring. Both macro- and microsegregation effects have been studied in these crystals in an attempt to understand the growth mechanism. Zinc distributions have been assessed by near-infrared transmission, X-ray lattice parameter measurements, atomic absorption spectrometry (AAS) and Auger electron spectrometry (AES). The last technique was used for the microsegregation studies, while AAS provides the absolute calibration for Zn content. Comparisons with segregation behaviour found in the literature will be given. It will be shown that the low temperature gradient and low growth rate lead to a degree of supercooling in the first-to-freeze region and this leads to significant Zn segregation in both radial and axial directions. As the crystals reach full diameter, the radial variation is decreased, presumably by the action of the ACRT, and axial segregation is also reduced.     

Genetic algorithms in optimization of system reliability

After initial production, improvements are often made to components of a system, to upgrade system performance; for example, when designing a later version or release. This paper presents an optimization model that identifies the types of component improvements and the level of effort spent on those improvements to maximize one or more performance measures (e.g., system reliability or availability) subject to constraints (e.g., cost) in the presence of uncertainty about the component failure rates. For each component failure mode, some possible improvements are identified along with their cost and the resulting improvement in failure rates for that failure mode. The objective function is defined as a stochastic function of the performance measure of interest-in this case, 5^th percentile of the mean time-between-failure distribution. The problem formulation is combinatorial and stochastic. Genetic algorithms are used as the solution method. Our approach is demonstrated on a case study of a personal computer system. Results and comparison with enumeration of the configuration space show that genetic algorithms perform very favorably in the face of noise in the output: they are able to find the optimum over a complicated, high dimensional, nonlinear space in a tiny fraction of the time required for enumeration. The integration of genetic algorithm optimization capabilities with reliability analysis can provide a robust, powerful design-for-reliability tool     

Factoring and reductions for networks with imperfect vertices

Factoring and reductions are effective methods for computing the K-terminal reliability of undirected networks, but they have been applied mostly to networks with perfect vertices. However, in real problems, vertices may fail as well as edges. Imperfect vertices can be factored like edges, but the complexity then increases exponentially with their number. A technique has been developed to account for the failure of vertices with small additional cost, using a modified method of factoring and reductions. This technique is very easy to integrate into a factoring algorithm. It consists of factoring not on a single element (e.g., a single edge) but on a set of elements (e.g., an edge and its endpoints). The problem is that random variables associated with the elements of the network are no longer independent. This can be handled by choosing factoring edges that have at least one perfect endpoint. This technique leaves the factoring algorithm practically unchanged. The only difference is that some supplementary probability values are kept for the imperfect vertices of the original and the induced graphs. For algorithms using simple reductions, it has negligible computational cost     

Optical Network Design With Mixed Line Rates and Multiple Modulation Formats

With the growth of traffic volume and the emergence of various new applications, future telecom networks are expected to be increasingly heterogeneous with respect to applications supported and underlying technologies employed. To address this heterogeneity, it may be most cost effective to set up different lightpaths at different bit rates in such a backbone telecom mesh network employing optical wavelength-division multiplexing. This approach can be cost effective because low-bit-rate services will need less grooming (i.e., less multiplexing with other low-bit-rate services onto high-capacity wavelengths), while a high-bit-rate service can be accommodated directly on a wavelength itself. Optical networks with mixed line rates (MLRs), e.g., 10/40/100 Gb/s over different wavelength channels, are a new networking paradigm. The unregenerated reach of a lightpath depends on its line rate. So, the assignment of a line rate to a lightpath is a tradeoff between its capacity and transparent reach. Thus, based on their signal-quality constraints (threshold bit error rate), intelligent assignment of line rates to lightpaths can minimize the need for signal regeneration. This constraint on the transparent reach based on threshold signal quality can be relaxed by employing more advanced modulation formats, but with more investment. We propose a design method for MLR optical networks with transceivers employing different modulation formats. Our results demonstrate the tradeoff between a transceiver's cost and its optical reach in overall network design.      

Failure analysis of evaporated metal interconnections at contact windows

An analysis of the open metallization problem at oxide steps at the surface of planar devices is described. This failure mechanism is essentially based upon the presence of a film discontinuity which grows during the evaporation process at the interface of coarse and dense crystal structures of the evaporated film. The growth rate of the coarse surface is somewhat larger than that of the normal surface. This mismatch in growth rates gives rise to the film discontinuity due to the self-shadowing effect by the former surface. The film discontinuity is apt to occur at the sharp step of phosphosilicate glass because of the following two reasons: 1) a large vapor-incidence angle to the perpendicular side wall; 2) a spontaneous growth of the coarse surface at the sharp edge of the step. Techniques investigated to improve the interconnection reliability include : 1) evaporation at elevated substrate temperature (∼300°C), 2) reduction of the thickness of phosphosilicate glass, 3)perpendicular vapor incidence to the substrate, and 4) protection of the discontinuity against corrosive agents.     

FFT and IMDCT circuit sharing in DAB receiver

This paper proposes a circuit-sharing approach to improve efficiency for the key digital audio broadcasting (DAB) techniques, i.e., MPEG1-audio decoding and orthogonal frequency division multiplexing (OFDM). Because OFDM's fast Fourier transform (FFT) requires heavy computational power for implementation, a single butterfly processing element (BPE) is adopted to reduce the chip area required for FFT. Furthermore, by modifying the BPE logical combinational circuit, both IMDCT (inverse modified discrete cosine transform) and FFT functions can be obtained simultaneously from a single VLSI chip. Therefore, the proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. The proposed circuit is simulated as a VLSI prototype chip using a 0.35 /spl mu/m CMOS process, with a chip area of about 22.09 mm/sup 2/ and a total gate count of approximately 10839 (excluding ROM and RAM).