300 mm Conversion challenge and breakthrough for future semiconductor manufacturing

The status regarding the planned conversion of the semiconductor industry to the larger and more productive 300 mm wafer size is reviewed. Many efforts are already underway to aid the conversion to 300 mm wafers. In addition to the consortiums in both U.S. and Japan, targeted at working with the equipment manufacturers and standard setting, SEMICONDUCTOR300, a joint venture between Motorola and Siemens, will develop a fully integrated process (64M/256M) on a complete toolset. Goal of the SC300 operation is to realize and demonstrate concepts to reduce the cost/die on 300 mm in comparison to 200 mm of approx. 30–40%. A financial model for semiconductor manufacturing using the larger substrates is offered along with the productivity opportunities for each of the equipment types. The authors define equipment manufacturers in terms of performance and financial targets. Achieving these targets is critical to making the conversion happen as well as determining the timing. Finally, the authors offer the breakthrough technologies expected to occur at the 300 mm production level. The noticeable difference between the 300 mm generation of wafer processing in comparison to previous 150 mm and 200 mm conversions is the increase in automation requirements. The 300 mm wafer size will change the way semiconductor factories operate. This presentation offers thoughts of what changes will be required to facilitate 300 mm wafers and beyond.     

Hemisphere-shaped silicon crystal wafers obtained by plastic deformation and preparation of their solar cells

Hemisphere-shaped crystal wafers can be prepared by the plastic deformation of Si crystal wafers. To obtain hemispherical Si wafers, graphite convex and concave dies were used. A Si wafer was set between dies and pressed at high temperatures. The Si wafer was pressed by an overweight of 200 N at various temperatures. The deformation regions in which well-shaped (100) and (111) wafers can be obtained by plastic deformation were determined using parameters of thickness and temperature. In order to demonstrate that the shaped wafers are of sufficiently high quality to be used in the preparation of devices, solar cells were fabricated using the hemispherical Si wafers pressed at 1,120°C and 1,200°C. The conversion efficiency of the hemispherical solar cells is 8.5–11.5%. It was clarified from the conversion efficiency of solar cells that the quality of the shaped crystal wafers can be improved by a proper annealing process. Thus, the hemispherical shaped wafers are of high quality to be used in the preparation of devices.     

300mm硅圆片的转移推动了半导体生产技术的进步

采用33mm硅圆片生产的集成电路要比硅圆片生产的集成电路增加30％－40％的利润收入。这对于低利润的DRAM和其它低利润积累的商业性产品起到了补救作用。目前这种观点已被许多生产半导体集成电路厂商所接受，并加速了向300mm硅圆片的转移。但转移到300mm硅片生产需投入150－200亿美元巨额资金，它迫使了世界所有的半导体制造商走共同合作、共担风险的道路。     

A new concept of p-(n-)/p-(n ) thin-film epitaxial silicon wafers for MOS ULSI's that ensuresexcellent gate oxide integrity

A new concept of epitaxial silicon (Si) wafers (NC epi) in which p ^-(n^-) thin-film layers are grown on p^-(n^-) Czochralski (CZ)-Si substrates (substrate resistivity: approximately 10 Ω cm) is proposed for metal oxide semiconductor (MOS) ultra large-scale integrated circuits (ULSI's) as a starting material. A thickness of 0.3-1 μm for the epitaxial layer (p ^-/p^- structure) is shown to be sufficient for improving the gate oxide integrity for MOS-ULSI's. The epitaxial layer grown on Si substrate greatly reduces weak spots in the gate oxide layer by covering microdefects in the CZ-Si represented by the crystal originated particle (COP). The p^-/p^$thin-film epitaxial structure results in very controlled resistivity for the electrically active region in the device, which in turn results in a lower growth cost and higher feasibility for use in current ULSI's. The features of NC epi in combination with proximity gettering is presented. An application of NC epi in shallow-trench isolation processes is discussed, considering the retrograde-type well-tub. The amenability of epitaxial wafers to wafer enlargement (over 300 mm) is discussed to eliminate the bad effects of COP     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

Sputter-deposition of NiMnSb magnetic thin films from a composite target onto Si substrates

We have deposited ferromagnetic NiMnSb thin films by sputtering from a single composite target onto Si wafer substrates. Similarly to earlier results using glass substrates, we find that a combination of low radio frequency power, low argon pressure, and moderate substrate temperature is successful at directly obtaining stochiometric, single-phase polycrystalline films with the bulk C1_b crystal structure. The use of Si substrates, however, is compatible with standard electronic processing and integration into electronic device structures. The similarity of the films to bulk NiMnSb suggests that the predicted half-metallic (100% spin-polarized) electronic properties of NiMnSb can be reproduced in a magnetically active thin-film device structure.     

Challenges for economical growth of high quality 300 mm CZ Si crystals

The changeover from 200 mm to 300 mm is required by the semiconductor industry due to the necessity for larger chip sizes and demand for decreasing cost. However, the cost for 300 mm crystal growth is likely to rise owing to larger puller, enlargement of hot zone, expensive silica crucibles and longer growth process times caused by lower growth rates and longer cooling rates. Simultaneously, the conditions are more complex and disadvantageous to the required higher qualities in comparison to smaller wafer diameters (e. g. position of OSF ring). This paper gives an overview about the challenges for 300 mm growth and approaches to provide appropriate solutions (e.g. application of magnetic systems, optimization of growth parameters by integration of numerical simulation).     

Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 μm. Problems associated with such ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 μm. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.     

High-Performance LWIR MBE-Grown HgCdTe/Si Focal Plane Arrays

We have been actively pursuing the development of long-wavelength infrared (LWIR) HgCdTe grown by molecular beam epitaxy (MBE) on large-area silicon substrates. The current effort is focused on extending HgCdTe/Si technology to longer wavelengths and lower temperatures. The use of Si versus bulk CdZnTe substrates is being pursued due to the inherent advantages of Si, which include available wafer sizes (as large as 300 mm), lower cost (both for the substrates and number of die per wafer), compatibility with semiconductor processing equipment, and the match of the coefficient of thermal expansion with silicon read-out integrated circuit (ROIC). Raytheon has already demonstrated low-defect, high-quality MBE-grown HgCdTe/Si as large as 150 mm in diameter. The focal plane arrays (FPAs) presented in this paper were grown on 100 mm diameter (211)Si substrates in a Riber Epineat system. The basic device structure is an MBE-grown p-on-n heterojunction device. Growth begins with a CdTe/ZnTe buffer layer followed by the HgCdTe active device layers; the entire growth process is performed in␣situ to maintain clean interfaces between the various layers. In this experiment the cutoff wavelengths were varied from 10.0 μm to 10.7 μm at 78 K. Detectors with >50% quantum efficiency and R ₀ A ∼1000 Ohms cm² were obtained, with 256 × 256, 30 μm focal plane arrays from these detectors demonstrating response operabilities >99%. Work supported by the Missile Defense Agency (MDA) through CACI Technologies, Inc. subcontract no. 601-05-0088, NVESD technical task order no. TTO-01, prime contract no. DAAB07-03-D-C214, (delivery order no. 0016)     

Effect of Prebonding Anneal on the Microstructure Evolution and Cu–Cu Diffusion Bonding Quality for Three-Dimensional Integration

Electroplated copper (Cu) films are often annealed during back-end processes to stabilize grain growth in order to improve their electrical properties. The effect of prebonding anneal and hence the effective initial grain size of the Cu films on the final bond quality are studied using a 300-nm-thick Cu film that was deposited on a 200-mm silicon (Si) wafer and bonded at 300°C. As compared with the control wafer pair with a prebonding anneal at 300°C for 1?h in N₂, the wafer pair without a prebonding anneal showed greater improvement in void density based on c-mode scanning acoustic microscopy (c-SAM). Dicing yield and shear strength were also enhanced when a prebonding anneal was not applied. This improvement is due to substantial grain growth of smaller Cu grains during the bonding process, which leads to a stronger Cu?CCu bond. Our work has identified a Cu?CCu bonding process with a lower total thermal budget, which is seen as a favorable option for future three-dimensional (3D) integrated circuit (IC) technology.     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

DNA-Based Strategies for Site-Specific Doping

The development of novel doping strategies compatible with high-resolution patterning and low cost, large-scale manufacturing is critical to the future development of electronic devices. Here, an approach to achieve nanoscale site-specific doping of Si wafer using DNA as both the template and the dopant carrier is reported. Upon thermal treatment, the phosphorous atoms in the DNA diffuse into Si wafer, resulting in doping within the region right around the DNA template. A doping length of 30 nm is achieved for 10 s of thermal treatment at 1000 °C. Prototype field effect transistors are fabricated using the DNA-doped Si substrate; the device characteristics confirmed that the Si is n-doped. It is also shown that this approach can be extended to achieve both n-type and p-type site-specific doping of Si by using DNA nanostructures to pattern self-assembled monolayers. This work shows that the DNA template is a dual-use template that can both pattern Si and deliver dopants.     

300 mm Epitaxy: challenges and opportunities from a wafer manufacturer’s point of view

Results on 300 mm silicon wafer epitaxy according to the 0.18 μm design rule requirements are presented. Wafer uniformity, surface metals, geometry, and thermal stability demonstrate production capabilities. Localized light scattering particles and crystal defects are identified as the largest technological challenge. Preliminary experiments indicate that industry’s requirements can be met. The p/p+ epitaxial wafer is the best candidate to meet the 300 mm cost challenge, as well as the technological requirements for integrated circuit manufacturing.     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Defect requirements for advanced 300 mm DRAM substrates

In the background of increasing requirements for advanced 300 mm DRAM substrates, the possibilities of balancing defect requirements versus cost and feasibility are discussed. For DRAMs based on deep trench capacitors, the main focus regarding defects is on voids, so-called crystal originated pits (COPs), which are present in the commonly used vacancy rich silicon crystals. Whereas for the material used for recent DRAM design rules, the typical COP sizes around 150 nm have still been sufficiently small not to deteriorate the yield of the DRAM products, for future design rules a reduction of COPs in the device active area will be required. Since the conversion to 300 mm wafers is purely cost driven, a solution has to be found for making 300 mm low defect wafers cost effective for the usage even on products under a high cost pressure like DRAM.A promising material option is 300 mm high temperature annealed wafers, which are on the one hand able to fulfil the future requirements in terms of performance and offer on the other hand also the potential to become a cost effective substrate by implementation of cost saving opportunities. The task of the wafer users is to critically review the requirements and to identify essential needs in contrast to “nice to have” items. For 300 mm annealed wafers, the requirements regarding COP reduction and slip performance are discussed.     

Stretchable Active Matrix Inorganic Light‐Emitting Diode Display Enabled by Overlay‐Aligned Roll‐Transfer Printing

An active matrix‐type stretchable display is realized by overlay‐aligned transfer of inorganic light‐emitting diode (LED) and single‐crystal Si thin film transistor (TFT) with roll processes. The roll‐based transfer enables integration of heterogeneous thin film devices on a rubber substrate while preserving excellent electrical and optical properties of these devices, comparable to their bulk properties. The electron mobility of the integrated Si‐TFT is over 700 cm² V^?1 s^?1, and this is attributed to the good interface between the Si channel and the thermally grown SiO₂ insulator. The light emission properties of the LED are of wafer quality. The resulting display stably operates under tensile strains up to 40%, over 200 cycles, demonstrating the potential of stretchable displays based on inorganic materials.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Transfer of metal MEMS packages using a wafer-level solder transfer technique

This paper presents a modular, low profile, wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the carrier wafer and TLP bonding of the cap to the device wafer during bonding. The bond and transfer cycle has a maximum temperature of 300/spl deg/C and lasts about 2.5 h. This approach has been demonstrated with nickel (Ni) caps as thin as 5 microns, with thicker caps certainly possible, ranging in size from 200 /spl mu/m to 1 mm. They were transferred with a lead-tin (Pb-Sn) solder layer and bonded with nickel-tin (Ni-Sn) TLP bonding with greater than 99% transfer yield across the wafer.     

Surface activation using oxygen and nitrogen radical for Ge-Si Avalanche photodiode integration

In this work, an alternative method for producing the single crystalline Ge-Si Avalanche photodiodes (APD) with low thermal budget was investigated. Structural and electrical investigations show that low temperature Ge to Si wafer bonding can be used to achieve successful APD integration. Based on the surface chemistry of the Ge layer, the buried interfaces were investigated using high resolution transmission electron microscopy as a function of surface activation after low temperature annealing at 200 and 300 °C. The hetero-interface was characterized by measuring forward and reverse currents.     

砂轮粒径对300 mm Si片双面磨削影响的研究

在直径300mmSi片制备过程中,利用双面磨削技术能获得高精度的表面参数,但同时却会在Si片表面留下明显的磨削印痕,这会影响Si片表面平整度.通过选择#2000和#3000砂轮对Si片进行磨削实验,获得两种型号砂轮磨削出Si片的形貌图、磨削印痕和局部平整度,并分别进行了比较.结果表明,选择粒度更细的#3000砂轮能够有效地弱化Si片表面的磨削印痕,同时改善边缘局部平整度差的问题,从而提高Si磨削片表面的局部平整度.