3D封装中的圆片减薄技术

随着微电子工业迅猛发展,圆片直径越来越大,当150mm、200mm甚至300mm英寸圆片被减薄到150μm以下时,圆片翘曲和边缘损伤问题变得尤为突出。超薄减薄技术是集成电路薄型化发展的关键技术,它直接影响电路的质量和可靠性。文章从超薄圆片减薄中常见的圆片翘曲和边缘损伤造成的损失出发,分析了圆片翘曲和边缘损伤的原因,提出了相应的改善措施。     

湿法刻蚀应对圆片减薄后翘曲问题的探讨

随着微电子产业的发展,圆片直径越来越大、厚度越来越薄。一些本来不被关注的问题逐渐凸现出来。当150mm、200mm甚至300mm的圆片被减薄到200μm或者200μm以下时,圆片本身的刚性将慢慢变得不足以使其保持原来平整的状态。文章从圆片减薄后产生翘曲的直观表象入手,分析了产生翘曲问题的根本原因,采用湿法刻蚀的方式去除了圆片因减薄形成的背面损伤层,改善了圆片减薄后的翘曲问题。     

300mm硅圆片的转移推动了半导体生产技术的进步

采用33mm硅圆片生产的集成电路要比硅圆片生产的集成电路增加30％－40％的利润收入。这对于低利润的DRAM和其它低利润积累的商业性产品起到了补救作用。目前这种观点已被许多生产半导体集成电路厂商所接受，并加速了向300mm硅圆片的转移。但转移到300mm硅片生产需投入150－200亿美元巨额资金，它迫使了世界所有的半导体制造商走共同合作、共担风险的道路。     

半导体设备市场的新动向

由于全球半导体市场温和增长和全球半导体资本支出市场从不缓至下滑,导致全球半导体设备市场增长放缓,2007年增长3%～4%,2008年可能出现下滑,中国台湾地区已成为全球第二大半导体设备、材料市场。光刻设备市场看好,2006～2012年复合年增长率将达到13%。450mm晶圆是半导体产业发展的必然趋势,向450mm晶圆过渡的最佳时间是2013年前后。     

Technology decisions to minimize 450-mm wafer size transition risk

About every ten years, the semiconductor industry has increased its wafer diameter size. This change, when coupled with device innovations such as transistor design improvements, new materials, and lithography feature size reductions, have enabled the semiconductor industry to reduce cost per function by /spl sim/30% each year over the past 30 years, while enabling factories to be highly productive. This paper outlines key factory attributes and technology decisions required to make the next wafer size conversion from 300to 450-mm wafers and provides a detailed examination of the factors that should be considered by integrated circuit (IC) makers, equipment suppliers, and consortia members as a team. We show a subset of these attributes that can be decided quickly, a list of attributes that need more analysis and discussion, and conclude with a vision of the capabilities that a 450-mm factory will have.     

Three hundred-mm wafers: a technological and an economical challenge

For the transition from 200- to 300-mm wafers, in addition to the technological challenges, there is the equivalent cost challenge to be met. The ultimate target is cost parity per unit area of silicon between 200 and 300 mm. The major blocking point to be cleared appears to be crystal pulling. The question of cost of crystal pulling is mainly related to the large crystal weights (>300 kg) and to the issue of crystal defects (crystal originated pits (COPs); voids in the Si crystal) generated by crystal pulling. An alternative route to address the defect problem is to use epitaxy to create a defect-free layer of Si for the active device regions. Close co-operation between wafer manufacturers and users is absolutely necessary to address these key issues. Furthermore, to contain cost, wafer makers and device manufacturers have to work together intensively to implement standardisation wherever possible and to avoid cost driving overspecifications (e.g. for front and backside particles or flatness).     

Challenges for economical growth of high quality 300 mm CZ Si crystals

The changeover from 200 mm to 300 mm is required by the semiconductor industry due to the necessity for larger chip sizes and demand for decreasing cost. However, the cost for 300 mm crystal growth is likely to rise owing to larger puller, enlargement of hot zone, expensive silica crucibles and longer growth process times caused by lower growth rates and longer cooling rates. Simultaneously, the conditions are more complex and disadvantageous to the required higher qualities in comparison to smaller wafer diameters (e. g. position of OSF ring). This paper gives an overview about the challenges for 300 mm growth and approaches to provide appropriate solutions (e.g. application of magnetic systems, optimization of growth parameters by integration of numerical simulation).     

300mm晶圆对半导体设备的挑战

300mm晶圆生产线必须采用新标准、新技术、新流程、新设备、新布局、新厂房和新设施等。因此,300mm晶圆向半导体设备提出了挑战。     

Automation and fab concepts for 300 mm wafer manufacturing

The introduction of 300 mm wafers into integrated circuit manufacturing will affect the design of the fabs. This paper covers the expectations of IC manufacturers and the progress in technology with respect to the fab itself and automation systems. The fab design is affected by the future use of closed wafer carriers, a consequent automation strategy, new challenges in contamination control, and the increased importance of environmental aspects. It will be described how these factors influence the fab design and the status of the discussed technologies.     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Transient thermal behavior in a new RTP chamber

The transient thermal behavior of 200 and 300 mm wafers in a new rapid thermal processing (RTP) chamber is investigated. The AST3000 is a new RTP tool to meet the process requirements for both wafer sizes in 0.18 μm technologies and beyond. In this paper, experimental results obtained on both 200 and 300 mm wafers for varying processing conditions are shown: spike anneal experiments with fast ramp rates up to 200°C/s were performed. For standard anneal recipes, the steady state time is varied in a broad range and also the inherent temperature uniformity is investigated.     

炉管制程工艺中的片数效应及其优化方案

随着半导体技术的发展,越来越多的立式炉管在200mm及300mm集成电路晶圆制造中被应用到。同时炉管制程中的片数效应随着集成电路芯片的集成度越来越高而被凸显出来。文章将以LPCVD氮化硅在0.16μm、64M堆叠式内存制造过程中的片数效应为例,阐述炉管制程工艺中的片数效应以及通过调整制程参数（温度、沉积时间）的方式予以解决的实例。文中通过调整炉管上中下的温度来补偿气体的分布不均匀,调整沉积时间来补偿不同片数的沉积速率的差异,两者结合并辅以基于片数的分片程式来解氮化硅电介质沉积的片数效应。同时以此为基础总结出炉管片数效应的解决方案。     

300mm硅片精密化学机械抛光机几何参数优化(英文)

对于评价用于极大规模集成电路(ULSI)生产的300 mm硅抛光片的表面质量,需要关注两个关键参数即:SFQR和GBIR。在中国电子科技集团第四十五研究所研发的中国第一台最终化学精密抛光机的验证过程中,我们发现为了提高硅片表面的几何参数,必须监控抛光前硅片的形貌,并根据不同的硅片表面形貌来改变抛光头的区域压力。通过深入分析抛光前硅片的表面形貌,我们发现当硅片形貌为凹陷形状时,抛光后的硅片表面将严重恶化。由此,根据每个硅片不同的形貌,我们用特殊设计的抛光头来调整背压的区域分布,然后再进行抛光。最终,经过抛光头区域压力调整后的硅片几何参数比调整前得到了大幅提升,并已经能够满足我们的产品指标并可以用于生产。     

Metaheuristic scheduling of 300-mm lots containing multiple orders

The standard unit of transfer in new semiconductor wafer fabrication facilities is the front opening unified pod (FOUP). Due to automated material handling system concerns, the number of FOUPs in a wafer fab is kept limited. Moreover, a certain number of new and larger 300-mm wafers will be placed in these FOUPs and this makes grouping orders from multiple customers into a job a necessity. Thereby, efficient utilization of the FOUP capacity while attaining good system performance is a challenge. We previously investigated optimization-based solution approaches for minimizing total weighted completion time and maximizing on-time delivery performance for the single machine multiple orders per job scheduling problem. We present two metaheuristic solution approaches for this scheduling problem under two different typical wafer fab machine environments: single unit processing and single lot processing. Experimental results demonstrate that the metaheuristic approaches can find near-optimal solutions for realistic-sized 300-mm scheduling problems in an acceptable amount of computation time.     

Advanced IX projection photolithography

Pattern techniques in the semiconductor industry are driven by the need to improve cost/performance per bit. The key to reducing cost per bit and improving performance is increased density. Tighter photolithography ground rules (smaller images with reduced line width and registration tolerances) are primary sources of increased density. Enhanced ground rules coupled with larger wafers are certain to form the basis for the next generation of VLSI chips. The trend toward tighter ground rules and larger wafers is causing many semiconductor manufacturers to migrate away from IX projection tools, the workhorses of present-day production lines, to step and repeat exposure tools. The higher numerical aperture of step and repeat tools, coupled with chip-by-chip focus, guarantees improved resolution compared to today’s IX projection tools. The price paid for increased numerical aperture is reduced field size and, subsequently, reduced throughput and higher exposure cost per wafer. Ideally, it would be preferable to improve the resolution of the IX projection tool/process to make it competitive with the step and repeat tool, while maintaining the high throughput of IX systems. Effective use of shorter exposure (< 350 nm) wavelengths in IX systems is the key to extending resolution capability.     

300 mm Si片加工及最新发展

65 nm及以下线宽对Si片表面的各方面性能要求越来越高,主要体现在两个方面,一个是加工工艺,另一个是加工设备.在加工方法上,65 nm线宽用300 mm Si片不同于90 nm,如运用多步单片精密磨削,不仅可以提高表面几何参数,还可以减小表面特别是亚表面的损伤层.而对于加工设备,要求更加精密,特别是单面精抛光,在保证去除量的同时还要使Si片表面各点的去除量保持均匀.对目前300 mm Si片的磨削、抛光及清洗的每一道工艺流程,特别是相对于65 nm技术的一些加工流程及方法的最新发展进行了详细的论述,指出了300 mm Si片加工工艺的发展趋势.     

Crystalline damage in silicon wafers and 'rare event' failure introduced by low-energy mechanical impact

We used X-ray diffraction imaging to detect and characterize mechanical damage introduced to 300 mm silicon wafers by low impact energy exerted on the wafer edge. Maps of crystalline damage show a correlation between the damage size, the magnitude of the impact energy and the location of the impact point. We demonstrate the existence of crystalline non-visual defects; crystalline defects that appear in the X-Ray diffraction images but not in optical microscopy or scanning electron microscope. We propose a mechanism of crystalline damage formation at low impact energies based on finite element analysis and high-resolution synchrotron white beam transmission X-ray topography. Finally, we propose the concept of 'rare-event' to described relatively low rate of occurrence of wafer failure by fracture within semiconductor manufacturing facilities.     

半导体晶圆化学镍/金UBM工艺与设备

介绍了半导体晶圆化学镍金UBM的工艺流程及其自动控制生产线,包括设备材料的要求及设备内部结构。在200mm的半导体晶圆上成功制作5μm化学镍/金UBM和18μm化学镍金凸点。在光学显微镜、表面轮廓仪和SEM下检测了化学镍/金镀层的表面形貌。通过EDX分析化学镍/金UBM中的镍磷含量。3D自动光学检测了200mm晶圆上化学镍/金凸点的高度和共面性,讨论了镍/金凸点的剪切强度和失效模式,分析了生产中化学镍/金UBM的两种常见缺陷及成因。     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

Quantifying the environmental footprint of semiconductor equipment using the environmental value systems analysis (EnV-S)

Many environmental and health impacts from semiconductor processing are tied to the design of the manufacturing equipment. Evaluating solutions to properly treat effluents from semiconductor tools has become an increasingly important part of supply chain management and equipment procurement decisions. Accordingly, understanding the environmental footprint associated with equipment sets is essential for both equipment manufacturers and semiconductor manufacturers seeking to improve their products' environmental and financial performance. Equipment environmental performance must be evaluated within the context of the factory infrastructure and auxiliary equipment sets, with appropriate allocations of impacts from additional steps, both upstream and downstream of the wafer processing tools (chemical precursor delivery as well as byproduct treatment). Several challenges to environmental assessments arise from the nature of semiconductor manufacturing itself, due to short process life cycles, complexity of processes, and the need to track diverse inter-related impacts. Environmental value systems analysis (EnV-S) is an analytical tool to evaluate the environmental performance of semiconductor processing. EnV-S develops environmental assessments through a "bottom-up" analysis approach, assembling equipment environmental models to describe a system. This paper presents the use of EnV-S as a tool to quantify the environmental impact of a product or process by creating an operational signature along multiple dimensions of cost and environmental and health factors. The use of EnV-S is illustrated through a case study comparing systems that abate emissions from dielectric chemical vapor deposition processes.