IBM 8265 ATM Backbone Switch software architecture

The IBM 8265 ATM Backbone Switch is the latest switch in the family of IBM ATM switches, designed for building large scale and reliable ATM network backbones. Two articles on the IBM 8265 ATM Backbone Switch are provided in this journal, describing the hardware architecture and the software architecture separately. This article describes the functions of the ATM Operating System and the ATM Multi-protocol Switched Services that run inside the IBM 8265 ATM switch. The focus is given to issues that are not addressed by the ATM Forum, and extensions that are needed when building ATM networks.     

ATM校园主干网下子网的互连方案

在ＡＴＭ校园主干网下如何使用ＡＴＭ技术把传统的以太子网互连起来，这是本文讨论的中心议题。在这种前提下，阐述了使用ＡＴＭ的三种标准协议来分别解决以太子网互连的几种方案，并进行了分析和比较。重点阐述了使用ＭＰＯＡ解决以太子网互连的技术。     

ATM交换机中的信元速率管制技术

本文根据ATM网络的传输特征，讨论了网络拥塞的可能性，详细介绍了使用虚拟调度算法的信元速率管制技术，并结合工程实际应用，给出了一种ATM交换机信元速率管制的设计方法。     

Modular multicast ATM switching architecture

A modular multicast packet switching architecture is proposed for the B-ISDN/ATM. In this switching architecture, we use the abilities of a broadcast bus suitable for multicasting services. Instead of using the concatenation of a copying network and a routing network, we use the same switching network to perform both copying and routing of multicast packets. This multicast switch architecture treats unicast and multicast packets in the same way; the delay time for these two kinds of packets has the same characteristics for the affective load in the switching. Through the modularity of this switching architecture, it is easy to dimension the switching system. We also include a mathematical analysis of this architecture.     

对ATM机互连障碍的分析

从聚集的难度及目前ＡＴＭＦｏｒｕｍＰＮＮＩ路由标准的不足等方面初步分析了ＡＴＭ交换机互连的障碍及其原因。     

校园主干网中的ATM与千兆以太网之争

本文叙述了ＡＴＭ与千兆以太网在校园主干网中各自的技术优势,并进行了多方面比较,最后阐述了未来网络技术的发展主流是ＡＴＭ与千兆以太网的并存技术。     

基于主干备份的ATM网络组网应用

本文分析了ATM网络中核心节点网络交换机的热备份方式,介绍了一种基于主干备份和路由备份的ATM网络的组网应用。本应用中,通过两台高性能Bay Networks 5005BM ATM交换机,以热备份方式组成核心节点,以星型方式连接二级交换机,组成了高可靠的网络平台。     

一种可提供QoS保证的交换结构

面向以太网的物理帧时槽交换（EPFTS）是四川省网络与通信技术重点实验室提出的“单物理层用户数据传输平台网络”中的关键技术,它是以“面向以太网的帧”为数据传输单元的高速交换技术,正是针对实现EPFTS而提出的交换结构方案。在对常用的交换结构和调度算法进行分析的基础上,针对EPFTS要达到的目标和技术特点,提出了一种能够在物理层交换中保证服务质量的交换结构,称为基于总线的、每输入-输出独立的输出缓存交换结构,同时提出了逻辑队列的排队策略,并对该结构进行了软件仿真。仿真结果表明,使用加权公平调度算法,提出的交换结构对实时业务可提供端到端的QoS保证,对非实时业务可提供最大-最小公平服务。     

VLSI hardware architecture for complex fuzzy systems

This paper presents the design of a VLSI fuzzy processor, which is capable of dealing with complex fuzzy inference systems, i.e., fuzzy inferences that include rule chaining. The architecture of the processor is based on a computational model whose main features are: the capability to cope effectively with complex fuzzy inference systems; a detection phase of the rule with a positive degree of activation to reduce the number of rules to be processed per inference; parallel computation of the degree of activation of active rules; and representation of membership functions based on α-level sets. As the fuzzy inference can be divided into different processing phases, the processor is made up of a number of stages which are pipelined. In each stage several inference processing phases are performed parallelly. Its performance is in the order of 2 MFLIPS with 256 rules, eight inputs, two chained variables, and four outputs and 5.2 MFLIPS with 32 rules, three inputs, and one output with a clock frequency of 66 MHz     

IBM RISC System/6000: architecture and performance

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given     

基于搜索式地址队列的漏斗形ATM交换

为了适应多媒体通信从实验室走向社会的需要,网络传输速度越来越快,交换机也必须以更快的速度、更大的规模进行交换。然而由于当前微电子技术水平的限制,ATM交换中缓冲器的访问速度成为主要的瓶颈。为了在现有的技术条件下实现高性能的交换,文章提出了一种称为“漏斗形多缓冲的ATM交换结构”。并行处理技术在该结构中得到充分的体现:(1)通过把多个较小规模的交换单元(NxM)平行放置,实现较大规模的交换系统(NxN);(2)将单一缓冲结构变为多缓冲结构,使在一信元周期内由一个缓冲器完成多次读/写操作变为由多个缓冲器来分担,从而使每个缓冲器的访问速度大大降低。在缓冲器控制方面,该交换系统采用了基于搜索式的地址队列,它具有在满足所需的服务质量的前提下,易于实现诸如多点广播和基于优先级服务等高级功能。     

ATM交换控制电路设计验证技术

异步传输模式(ATM)技术作为宽带应用的基本技术用在局域网和广域网中。该文结合ATM技术应用,以ATM交换机的一组芯片设计为研究对象,针对其中一款ATM交换控制电路的FPGA原型,提出一种基于Tcl语言的自动化验证方法,实现ATM交换控制电路的功能验证。应用结果表明：话音业务和IP业务均通信正常,中继信令测试正常。     

Elliptic curve based hardware architecture using cellular automata

This study presents an efficient division architecture using restricted irreducible polynomial on elliptic curve cryptosystem (ECC), based on cellular automata. The most expensive arithmetic operation in ECC is division, which is performed by multiplying the inverse of a multiplicand. The proposed architecture is highly regular, expandable, and has reduced latency and hardware complexity. The proposed architecture can be efficiently used in the hardware design of crypto-coprocessors.     

Adaptive Routing on the New Switch Chip for IBM SP Systems

The IBM RS/6000 SP is one of the most successful commercially available multicomputers. SP owes its success partially to the scalable, high bandwidth, low latency network. This paper describes the architecture of Switch2 switch chip, the recently developed third generation switching element which future IBM RS/6000 SP systems may be based on. Switch2 offers significant enhancements over the existing SP switch chips by incorporating advances in both VLSI technology and interconnection network research. One of the major new features of Switch2 is the incorporation of adaptive routing support into it. We describe the adaptive source routing architecture of the Switch2 chip which is a unique feature of this chip. The performance of the adaptive source routing and oblivious routing for a wide range of system characteristics and traffic patterns is evaluated. It is shown that adaptive source routing outperforms or performs comparably with oblivious routing. We propose two novel algorithms for generating adaptive routes specifications required for enabling the usage of adaptive source routing. A comparison between the cost of these two algorithms and the performance improvement obtained from using these algorithms are discussed. We also propose different output selection functions to be used in switching elements for implementing the adaptive routing. We evaluate and compare the performance of these selection functions and discover that the best selection functions for BMINs are not dependent on the traffic pattern, message size, or system size.     

A flat wireless ATM LAN architecture with distributed ATM switching in base stations

The infrastructure for cellular wireless ATM systems is normally assumed to be hierarchical with the ATM switching functionality being provided by centralised ATM switches. For easy installation of the infrastructure, a flat architecture is proposed for cellular wireless ATM LAN, which is enabled by a distributed ATM switch concept. In this concept, a smart ATM switching component is embedded into the wireless access point. The same component is used for a fixed ATM access point, too. A number of such switching components are connected in a ring topology to form the ATM backbone. A ring control protocol hides the ring-specific features from the user and assures that a standardised UNI is provided to any wireless and fixed terminal.     

ATM以太网接入交换机的网络管理模型及其实现

本文介绍了把高速交换技术应用于局域网的ATM以太网接入交换机的软件体系结构模型和SNMP网络管理模型,以及在国家“九五”重点科技攻关专题LT－30－1 ATM以太网接入交换机上如何开发SNMP代理。     

Real-time scalable hardware architecture for 3D-HEVC bipartition modes

This article presents a real-time scalable hardware architecture for the bipartition modes of 3D high-efficiency video coding (3D-HEVC) standard, which includes the depth modeling modes 1 (DMM-1) and 4 (DMM-4). A simplification of the DMM-1 algorithm was done, removing the refinement step. This simplification causes a small BD-rate increase (0.09 %) with the advantage of better using our hardware resources, reducing the necessary memory required for storing all DMM-1 wedgelet patterns by 30 %. The scalable architecture can be configured to support all the different block sizes supported by the 3D-HEVC and also to reach different throughputs, according to the application requirements. Then, the proposed solution can be efficiently used for several encoding scenarios and many different applications. Synthesis results considering a test case show that the designed architecture is capable of processing HD 1080p videos in real time, but with other configurations, higher resolutions are also possible to be processed.     

多种哈希算法的可重构硬件架构设计

针对现有的哈希算法硬件架构仅实现少量几种算法的问题,设计了一种可实现SM3,MD5,SHA-1以及SHA-2系列共7种哈希算法的可重构IP,以满足同一系统对安全性可选择的需求。通过分析各哈希算法及其运算逻辑的相似性,该设计最大化地重用加法器和寄存器,极大地减少了总的实现面积。此外,该设计灵活可配,可以对内存直接存取。以Altera的Stratix II为FPGA目标器件,其最高频率可达100 MHz,总面积较现有设计减少26.7%以上,且各算法单位面积吞吐率均优于现有设计。     

AES算法的可配置硬件结构设计与实现

在分析AES算法的基础上,介绍了该算法各模块的设计实现方法,并将加解密运算结构设计为1个统一的结构。通过对密钥生成算法的分析,将3种密钥长度的密钥生成算法进行了可配置设计,使该设计能够实现加解密功能。该设计通过了FPGA仿真验证,与传统设计方案相比大大减小了硬件资源的消耗。