Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Evaluation of layer properties of effective parameters of metallic rod metamaterials in GHz frequencies

In this paper, analytical modeling and numerical simulation of the complex effective dielectric, magnetic constants and refractive index of a metallic rod metamaterial in microwave frequency range are presented. Analytical modeling has been done using modified mathematical models of the complex dielectric and magnetic constants obtained for rod metamaterial structure. Numerical simulation of the above-mentioned parameters has been made using S-parameters obtained with the help of finite-difference time-domain (FDTD) calculations. The numerical simulation has been carried out for different thickness of rods. Remarkable coincidence between analytical and numerical results was found. The effective dielectric constant enhancement of the considered composite has been obtained. Recommendations for the practical application of considered metamaterial structure for designing patch antennas have been discussed.     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

海洋激光雷达实验与仿真结果的对比

海洋激光雷达是探测上层海水并构建海洋立体观测网络的重要遥感设备。文中将激光雷达实验数据与MC (Monte Carlo)仿真、解析模型、原位数据进行综合对比,检验它们的匹配程度。与实验实测的激光雷达回波信号相比,MC仿真和解析模型均有很高的一致性(R^2>0.97),将原位漫射衰减系数(Kd)近似代入普通激光雷达方程也有较好的一致性(R^2>0.92)。反演得到的激光雷达衰减系数(α)表现出了相似的结果,MC仿真和解析模型具有更佳的一致性。结果表明:海洋激光雷达实验结果能与MC和解析模型的仿真结果很好地匹配。     

复合介质层SOI高压器件电场分布解析模型

提出复合介质埋层SOI(compound dielectric buried layer SOI,CDL SOI)高压器件新结构,建立其电场和电势分布的二维解析模型,给出CDL SOI和均匀介质埋层SOI器件的RESURF条件统一判据.CDL SOI结构利用漏端低k(介电常数)介质增强埋层纵向电场,具有不同k值的复合介质埋层调制漂移区电场,二者均使耐压提高.借助解析模型和二维数值仿真对其电场和电势进行分析,二者吻合较好.结果表明,对低k值为2的CDL SOILDMOS,其埋层电场和器件耐压分别比常规SOI结构提高了82%和58%.     

复合介质层SOI高压器件电场分布解析模型

提出复合介质埋层SOI(compound dielectric buried layer SOI,CDL SOI)高压器件新结构,建立其电场和电势分布的二维解析模型,给出CDL SOI和均匀介质埋层SOI器件的RESURF条件统一判据.CDL SOI结构利用漏端低k(介电常数)介质增强埋层纵向电场,具有不同k值的复合介质埋层调制漂移区电场,二者均使耐压提高.借助解析模型和二维数值仿真对其电场和电势进行分析,二者吻合较好.结果表明,对低k值为2的CDL SOILDMOS,其埋层电场和器件耐压分别比常规SOI结构提高了82%和58%.     

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

This paper proposes a new two dimensional（2D） analytical model for a germanium（Ge） single gate silicon-on-insulator tunnel field effect transistor（SG SOI TFET）. The parabolic approximation technique is used to solve the 2D Poisson equation with suitable boundary conditions and analytical expressions are derived for the surfacepotential,theelectricfieldalongthechannelandtheverticalelectricfield.Thedeviceoutputtunnellingcurrent is derived further by using the electric fields. The results show that Ge based TFETs have significant improvements inon-currentcharacteristics.Theeffectivenessoftheproposedmodelhasbeenverifiedbycomparingtheanalytical model results with the technology computer aided design（TCAD） simulation results and also comparing them with results from a silicon based TFET.     

Gate dielectric engineering of quarter sub micron AlGaN/GaN MISHFET: A new device architecture for improved transconductance and high cut-off frequency

In this paper analytical modeling for a novel three region gate dielectric engineered AlGaN/GaN Metal Insulator Semiconductor heterostructure field effect transistor (MISHFET) device architecture is presented which shows high transconductance and enhanced cut-off frequency at quarter micron gate lengths. Using a three region analysis along the horizontal direction in the gate dielectric region the expressions for transconductance and cut-off frequency of the device are obtained. It has been observed that using these gate dielectric schemes, improvements on device performance are observed over conventional MISHFET structures. Relative comparison of T and Γ-gate shaped structures is done with uniform gate dielectric profile and enhancement in microwave performance is observed. The proposed model is capable of modeling electrical characteristics like drain current, output conductance and threshold voltage of various other existent structures like uniform gate dielectric MISHFETs, HFETs and T-gate HFETs. The present model is based on closed form expression and does not involve any fitting parameter. The results obtained are compared with experimental data and show excellent agreement, thereby proving the validity of the model.     

Exact analytical model of single electron transistor for practical IC design

This paper presents a new exact analytical model for single electron transistor (SET) applicable for circuit simulation. It has been developed based on orthodox theory of single electronics using master equation where a scheme has been suggested to determine the most probable occupied electron states. The proposed model is more flexible and is valid for single or multi-gate, symmetric or asymmetric devices and can also consider the background charge effect. It can be used for large drain-source voltage range whatever the device is biased under symmetric or asymmetric bias conditions. SET characteristics produced by the proposed model have been verified against widely accepted single electron circuits Monte Carlo simulator SIMON and show a good agreement. Moreover, the model has been implemented in a widely used commercial circuit simulator SPICE to enable simulation with conventional electronic elements and a single electron inverter has been simulated and verified with SIMON results.     

A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs

A new two-dimensional (2-D) analytical model for the threshold voltage of a fully depleted short-channel Si-MESFETs fabricated on the silicon-on-insulator (SOI) has been presented in this paper. The 2-D potential distribution functions in the active layer of the device is approximated as a parabolic function and the 2-D Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. The calculations have been carried out for both uniform and nonuniform doping profiles in two dimensions. The minimum bottom potential is used to monitor the drain-induced barrier lowering effect and consequently an analytical expression for the threshold voltage of the device has been derived. The numerical results for the bottom potential and threshold voltage considering a wide range of device parameters have also been presented. The model has been compared with the simulated results obtained by using the ATLAS Device Simulation Software to show the validity of the proposed model. For uniform doping profile, the numerical results have also been compared with the reported data in the literature and a good agreement is observed among the three. The proposed model is simple and easy to understand the behavior of the fully depleted short-channel SOI-MESFETs as compared to the other models reported in the literature.     

Modeling and simulation of nanoscale tri-gate MOSFETs including quantum effects

Quantum effects are predominant in tri-gate MOSFETs, so a model should be developed. For the first time, this paper presents the analytical model for quantization effects of thin film silicon tri-gate MOSFETs by using variational approach. An analytical expression of the inversion charge distribution function（ICDF） or wave function for the tri-gate MOSFETs has been obtained. This obtained ICDF is used to calculate the important device parameters, such as the inversion charge centroid and inversion charge density. The results are validated against with the simulation data.     

A compact LDD MOSFET I-V model based on nonpinned surface potential

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.     

Numerical Study of Cascadability Performance of Continuous Spectrum Wavelength Blocker/Selective Switch at 10/40/160 Gb/s

Wavelength selective switches (WSS) and wavelength blockers (WB) are crucial elements in reconfigurable optical add-drop multiplexers and cross-connect nodes. For the "continuous spectrum" WB/WSS (CS-WB/WSS), the overall filtering passband of the WSS device can be adjusted in a quasi-continuous way by grouping two or more adjacent pixels offering enhanced switching flexibility at arbitrary channel spacing or multiline rates. However, loss and group delay ripples appear at each slot boundary causing degradations to the transmitted signal. In this paper, a system perspective analytical model has been developed. Through this model and detailed simulation studies, the relative impact of each imperfection on the overall cascadability performance of the WB/WSS is investigated. Different switching scenarios at various line rates (10, 40, and 160 Gb/s) have been considered and the corresponding specifications for the WSS device have been identified     

具有复合k介质埋层的高压SOI器件解析模型

An analytical model for a novel high voltage silicon-on-insulator device with composite-k(relative permittivity) dielectric buried layer(CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k(k D 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage(BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional(2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI(LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.     

Simultaneous switching noise analysis using application specific device modeling

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and /spl alpha/-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.     

A coherent scattering model to determine forest backscattering inthe VHF-band

A coherent scattering model to determine the forest radar backscattering at VHF frequencies (20-90 MHz) has been developed. The motivation for studying this frequency band is the recent development of the CARABAS Synthetic Aperture Radar (SAR). In order to model the scattering from branches and trunks, homogeneous dielectric cylinders placed above a semi-infinite di-electric ground have been analyzed. An analytical approach, where the theoretically exact currents induced in an infinite cylinder are truncated, has been compared to a numerical solution using the finite difference time domain (FDTD) method. If the first-order coherent ray tracing is included in the analytical approach, the results match well with the numerically exact FDTD solution. The results show that, in order to determine the VHF-backscattering from a forest stand, the coherent ground interaction is an important part and has to be considered. In this paper, modeling results are in good agreement with CARABAS measurements     

A new static induction thyristor (SITh) analytical model

In this paper, an analytical static induction thyristor (SITh) model is proposed based on device internal physical operating mechanisms. The nonquasi-static model predicts both device static and dynamic characteristics. The model accounts for effects of the device structure, lifetime, and temperature. Implemented in PSPICE as a subcircuit, model simulation results are compared with numerical simulation and experiment results for various electrical and thermal conditions. The model exhibits accurate results, good convergence, and fast simulation speed     

A new SOI high voltage device based on E-SIMOX substrate

A new NI (n+ charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration n+-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (Ev) are located in the spacing of two neighboring n+-regions on the interface by the force from lateral electric field (EL) and the compositive operation of Coulomb's forces with the ionized donors in the undepleted n+-regions. This effectively enhances the electric field of dielectric buried layer (EI) and increases breakdown voltage (Vb). An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.