Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the $DeltaSigma$ modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of $-$ 70 dBc and a worst-case in-band fractional spur power of $-$64 dBc.      

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-$N$ PLL utilizing a low-bit high-order $DeltaSigma$ modulator is presented. A 4-bit fourth-order $DeltaSigma$ modulator not only performs non-dithered 16-modulo fractional-$N$ operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8–2.6 GHz fractional-$N$ PLL is implemented in 0.18 $mu{hbox {m}}$ CMOS. By employing high-order deterministic $DeltaSigma$ modulation and hybrid spur compensation, the spur level of less than $-$55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

A High-Throughput Maximum a Posteriori Probability Detector

This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13$ mu{hbox {m}}$ CMOS technology and has a core area of 7.1 ${hbox {mm}}^{2}$.      

LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS

A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is achieved by switching mutual inductances within the inductor coil of the LC oscillator. To minimize resistive switching losses, the inductor coil consists of a non-switchable primary coil and two isolated secondary coils with series switches. When the switches are closed, the overall inductance reduces because of the switched mutual inductances. Three inductor bands, each consisting of 16 switched capacitor sub-bands, span a frequency range from 7.3 to 17.5 GHz. The in-band phase noise measured after a 1/4 divider is better than ${-}$107 dBc/Hz at 1 MHz offset frequency in the entire locking range. The PLL is fully differential and its core has a power consumption of 25 mW at the highest oscillation frequency.      

Finite-Element Analysis of Ex Vivo and In Vivo Hepatic Cryoablation

Cryoablation is a widely used method for the treatment of nonresectable primary and metastatic liver tumors. A model that can accurately predict the size of a cryolesion may allow more effective treatment of tumor, while sparing normal liver tissue. We generated a computer model of tissue cryoablation using the finite-element method (FEM). In our model, we considered the heat transfer mechanism inside the cryoprobe and also cryoprobe surfaces so our model could incorporate the effect of heat transfer along the cryoprobe from the environment at room temperature. The modeling of the phase shift from liquid to solid was a key factor in the accurate development of this model. The model was verified initially in an ex vivo liver model. Temperature history at three locations around one cryoprobe and between two cryoprobes was measured. The comparison between the ex vivo result and the FEM modeling result at each location showed a good match, where the maximum difference was within the error range acquired in the experiment (< 5 degC). The FEM model prediction of the lesion size was within 0.7 mm of experimental results. We then validated our FEM in an in vivo experimental porcine model. We considered blood perfusion in conjunction with blood viscosity depending on temperature. The in vivo iceball size was smaller than the ex vivo iceball size due to blood perfusion as predicted in our model. The FEM results predicted this size within 0.1-mm error. The FEM model we report can accurately predict the extent of cryoablation in the liver.     

Comparisons Between the p--q and p--q--r Theories in Three-Phase Four-Wire Systems

This paper presents a comparative analysis between results from applications of the p-q and the p-q-r theories in shunt active power filters for three-phase four-wire systems, discussing aspects related to the influence of the system voltage in the control methods that calculate the compensating currents. It is shown that in some cases, a preprocessing of the system voltage is required if the goal is to achieve sinusoidal compensated currents. On the other hand, when the goal is to compensate zero-sequence current, the need of energy storage elements in the active filter is discussed. In this case, if zero-sequence components are present simultaneously in the system voltage and load current, they produce zero-sequence power flow, and the control methods based on both theories must contain additional calculations to allow the elimination of energy storage elements in the active filter. A control strategy based on the p-q theory is proposed to eliminate the neutral current without the need of energy storage elements, with the advantage of avoiding the extra transformation from alphabeta0 to pqr coordinates that is needed in the p-q-r theory. Simulation results are presented for the purpose of comparing the performance of both control methods.     

Dual-Band LC VCO Architecture With a Fourth-Order Resonator

A dual-band LC voltage-controlled oscillator (VCO) architecture suitable for GSM/PCS/DCS applications is presented. The VCO utilizes a fourth-order resonance tank and avoids quality-factor-deteriorating switches. The paper outlines the design tradeoffs and the VCO when using a fourth-order resonator. The 0.8-GHz/1.8-GHz test chip was fabricated in the 0.5-mum IBM-5AM SiGe process and has achieved phase noise of -134 dBc/Hz at a 1-MHz frequency offset from the carrier, with 56-MHz and 121-MHz tuning ranges in the corresponding bands. The VCO core consumes 15 mW from a 2.5-V power supply     

In-Vitro and In-Vivo Trans-Scalp Evaluation of an Intracranial Pressure Implant at 2.4 GHz

Elevation of intracranial pressure is one of the most important issues in neurosurgery and neurology in clinical practice. The prevalent techniques for measuring intracranial pressure require equipments that are wired, restricted to a hospital environment, and cause patient discomfort. A novel method for measuring the intracranial pressure is described. A wireless completely implantable device, operating at an industrial-scientific-medical band of 2.4 GHz, has been developed and tested. In-vitro and in-vivo evaluations are described to demonstrate the feasibility of microwave pressure monitoring through scalp, device integrity over a long period of time, and repeatability of pressure measurements. A distinction between an epidural and sub-dural pressure monitoring techniques is also described. Histo-pathological results obtained upon a long-term device implantation favor the utilization of the sub-dural pressure monitoring method. On the other hand, in-vivo studies illustrate a maximum pressure reading error of 0.8 mm middot Hg obtained for a sub-dural device with a capacitive microelectromechanical system sensor compared to 2 mm middot Hg obtained for an epidural device with a piezoresistive sensor.     

In Vivo Impedance Imaging With Total Variation Regularization

We show that electrical impedance tomography (EIT) image reconstruction algorithms with regularization based on the total variation (TV) functional are suitable for in vivo imaging of physiological data. This reconstruction approach helps to preserve discontinuities in reconstructed profiles, such as step changes in electrical properties at interorgan boundaries, which are typically smoothed by traditional reconstruction algorithms. The use of the TV functional for regularization leads to the minimization of a nondifferentiable objective function in the inverse formulation. This cannot be efficiently solved with traditional optimization techniques such as the Newton method. We explore two implementations methods for regularization with the TV functional: the lagged diffusivity method and the primal dual–interior point method (PD-IPM). First we clarify the implementation details of these algorithms for EIT reconstruction. Next, we analyze the performance of these algorithms on noisy simulated data. Finally, we show reconstructed EIT images of in vivo data for ventilation and gastric emptying studies. In comparison to traditional quadratic regularization, TV regulariza tion shows improved ability to reconstruct sharp contrasts.      

Digital Wireless—Regulation and Control Free?

Considers how different our present state of technological prowess would be if wireless systems had not been discovered and implemented, then forecasts where we are headed in the real world and what the role of government and regulators may be.     

High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals

In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 10⁸ s for 13% charge loss).     

A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K _VCO) and the frequency step per a capacitor bank code (f _step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply.     

Low Phase Noise Self-Switched Biasing CMOS LC Quadrature VCO

A self-switched biasing quadrature voltage-controlled oscillator (VCO) is presented. It is implemented by directly injecting the oscillation signal of one VCO core into the other VCO core through the divided tail current sources without additional active devices for coupling. The proposed coupling structure automatically switches the NMOS field-effect transistors used in VCO cores and current sources from strong inversion to accumulation. Since the deep switching of MOSFETs was reported to physically reduce flicker noise, the proposed quadrature VCO (QVCO) is expected to improve the phase noise performance, which is confirmed experimentally. The designed QVCO using 0.18- $mu{hbox{m}}$ CMOS technology operates from 1.86 to 2.2 GHz with a 17% frequency tuning range. The measured phase noise is from $-$ 129.1 to $-$ 134.5 dBc/Hz at a 1-MHz offset, which is really close to ideal simulation results with the NMOS model disabling the flicker noise components. The average measured phase noise is 7.2 dB below the simulated one with a flicker noise model, which verifies the physical reduction of flicker noise by deep switching of the MOSFET. The phase noise figure-of-merit ranges from 179 to 185 over the entire tuning range. The QVCO dissipates 20 mA from a 1.8-V supply.      

A Novel Driving Scheme for Synchronous Rectifiers in LLC Resonant Converters

This paper proposes a novel synchronous rectifier (SR) driving scheme for resonant converters. It is very suitable for high-frequency, high-efficiency, and high-power-density dc–dc resonant converters with SRs. In this paper, an LLC resonant converter with the proposed synchronous rectification is designed and analyzed. With the proposed driving scheme, the SR body diode conduction is reduced to almost zero. The driving scheme eliminates the reverse-recovery problem of SRs. Both current and voltage stresses are greatly decreased, and the conduction loss and switching loss of SRs are also reduced considerably. The experimental results show that the proposed LLC resonant converter with SRs can achieve low stress, high efficiency, and high power density.      

An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters

This paper presents a scheme to accurately tune the quality factor of second-order LC bandpass filters. The information of the magnitude response at the center and one of the cutoff frequencies is used to tune both the amplitude and the quality factor of the filter using two independent yet interacting loops. Furthermore, the synergic interaction between the loops makes the proposed scheme stable and insensitive to the mismatch between the input amplitudes. A chip prototype was implemented in a 0.35-mum CMOS process and consumes 4.3 mA from a single 1.3-V supply. Measurement results show that at 1.97 GHz the quality factor is tunable from 60 to 220 while the amplitude is tunable between -15 and 0 dBm with worst case quality factor and amplitude tuning accuracies of 10% and 7%, respectively     

Explicit Model-Predictive Control of a PWM Inverter With an LCL Filter

This paper deals with the control of pulsewidth modulation inverters connected to the grid through resonant LCL filters. It proposes two alternative (piecewise affine) models that account for the switched behavior of the converter. Based on these improved models, an explicit model-predictive control scheme is derived in order to provide a fast response, making it very suitable for applications, such as active filtering, where a large bandwidth is required. A state observer and a grid voltage estimator are used in order to reduce the number of required sensors and to eliminate noise. The control scheme relies only on filtered current measurements and on the dc voltage.      

An In Vitro Model of a Retinal Prosthesis

Epiretinal prostheses are being developed to bypass a degenerated photoreceptor layer and excite surviving ganglion and inner retinal cells. We used custom microfabricated multielectrode arrays with 200-mum-diameter stimulating electrodes and 10-mum-diameter recording electrodes to stimulate and record neural responses in isolated tiger salamander retina. Pharmacological agents were used to isolate direct excitation of ganglion cells from excitation of other inner retinal cells. Strength-duration data suggest that, if amplitude will be used for the coding of brightness or gray level in retinal prostheses, shorter pulses (200 mus) will allow for a smaller region in the area of the electrode to be excited over a larger dynamic range compared with longer pulses (1 ms). Both electrophysiological results and electrostatic finite-element modeling show that electrode-electrode interactions can lead to increased thresholds for sites half way between simultaneously stimulated electrodes (29.4 plusmn 6.6 nC) compared with monopolar stimulation (13.3 plusmn 1.7 nC, < 0.02). Presynaptic stimulation of the same ganglion cell with both 200- and 10- m-diameter electrodes yielded threshold charge densities of 12 plusmn 6 and 7.66 plusmn 1.30 nC/cm², respectively, while the required charge was 12.5 plusmn 6.2 and 19 plusmn 3.3 nC.     

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range

Quadrature injection-lockedLC dividers with either a Miller topology or an injection-lockedLC VCO topology are coupled with transconductors to enhance their locking range. The effect of the transconductance coupling is analyzed theoretically and through circuit simulation. Both topologies were fabricated by 90-nm CMOS technology with a target input center frequency of 20 GHz and output frequency of 10 GHz. The measured locking range for the Miller topology with transconductance coupling is 25.3%, compared to 20.9% without coupling. The measured locking range for the injection-locked LC VCO topology with transconductance coupling is 18.1%, compared to 12.9% without coupling. Moreover, power consumption for both dividers is 6.4 mW with a 1.2-V supply.     

Adaptive Impedance-Matching Techniques for Controlling L Networks

The link quality of mobile phones suffers from antenna mismatch due to fluctuating body effects. Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch. To secure reliable convergence, a cascade of two control loops is proposed for independent control of the real and imaginary parts of impedance. A secondary feedback path is used to enforce operation into a stable region when needed. These techniques exploit the basic properties of tunable series and parallel LC networks. A generic quadrature detector that offers a power-independent orthogonal reading of the complex impedance value is presented, which is used for direct control of variable capacitors. This approach renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna-matching modules.