Utilization of an electron beam resist process to examine theeffects of asymmetric gate recess on the device characteristics ofAlGaAs/InGaAs PHEMTs

The DC and microwave characteristics of two sets of AlGaAs/InGaAs PHEMTs having a gate length of 0.2 μm are compared. The first set is composed of devices fabricated using a trilayer electron beam resist process for T-gate recess and metallization. The second set is composed of devices fabricated using a new four-layer electron beam resist process which enables the asymmetric placement of a T-gate in a wide recess trench. Devices fabricated using the four-layer resist process showed improved breakdown voltage, lower gate-drain feedback capacitance, lower output conductance, and higher f_max with only slight reduction of drain current and transconductance. For example, the off-state drain-source breakdown voltage increased from 5.2 to 12.5 V, and the f_max, increased from 133 to 158 GHz as the drain side cap recess, L_ud, was increased from 0 to 0.55 μm     

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT with asilicon interface control layer showing high DC- and RF-performance

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 μm. As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f_T, of 9 GHz and the maximum oscillation frequency, f_max, of 38 GHz were obtained for the 1.6 μm-gate-length device     

High performance double-doped InAlAs/InGaAs/InP heterojunction FET with potential for millimetre-wave power applications

Lattice matched InAlAs/InGaAs/InP heterojunction field-effect transistors (HJFETs), which have carrier supplying layers on and beneath the undoped InGaAs channel layer, have been successfully fabricated. A selective recess of the InGaAs channel edge at a mesa sidewall together with the use of a wide recess gate structure leads to a 5.7 V gate-drain breakdown voltage without kink effects. The fabricated HJFET with a 0.15*100 mu m/sup 2/ T-shaped gate exhibits a 700 mA/mm maximum drain current, a voltage gain of 14, and a 345 GHz maximum frequency of oscillation.<>     

Metamorphic InAlAs/InGaAs HEMTs on GaAs substrates with a novelcomposite channels design

We report on fabrication and performance of novel 0.13 μm T-gate metamorphic InAlAs/InGaAs HEMTs on GaAs substrates with composite InGaAs channels, combining the superior transport properties of In_0.52Ga_0.48As with low-impact ionization in the In_0.32Ga_0.68As subchannel. These devices exhibit excellent DC characteristics, high drain currents of 750 mA/mm, extrinsic transconductances of 600 mS/mm, combined with still very low output conductance values of 20 mS/mm, and high channel and gate breakdown voltages. The use of a composite InGaAs channels leads to excellent cut-off frequencies: f_max of 350 GHz and an f_T 160 GHz at V_DS=1.5 V. These are the best microwave frequency results ever reported for any FET on GaAs substrate     

Optimization of gate-to-drain separation in submicron gate-lengthmodulation doped FET's for maximum power gain performance

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g_m/g_o), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c_oμ_n product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g_m/g_o ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f_r) and the maximum frequency of oscillations (f _max) on the gate-to-drain separation (L_gd). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 μm, 0.15 μm and 0.1 μm are considered for analyses. The optimum values of L_gd calculated are 600 Å, 420 Å, and 340 Å for the corresponding maximum f_max-values of 250, 370, and 480 GHz, respectively     

InGaAs/InAlAs HEMT with a strained InGaP Schottky contact layer

The authors have fabricated an InGaAs/InAlAs HEMT structure with a strained InGaP Schottky contact layer to achieve selective wet gate recess etching and to improve reliability for thermal stress. Strained In_0.75Ga_0.25P grown on InAlAs has been revealed to have sufficient Schottky barrier height for use as a gate contact. Threshold voltage standard deviation has been reduced to one fifth that of a conventional InGaAs/InAlAs HEMT, as a result of successful selective recess etching. After thermal treatment at 300°C for 5 min, the drain current and transconductance did not change, while those of the conventional HEMT decreased by more than 10%     

Recess dependent breakdown behavior of GaAs-HFETs

GaAs based HEMT devices were fabricated with a constant recess towards the source, whereas the recess width towards the drain was varied. While the off-state breakdown voltage has been improved by the use of a wide recess towards the drain, no dependence of the on-state breakdown on the recess configuration was observed. The constant breakdown voltage in the on-state is analysed by the feedback parameters obtained from an extraction of the small signal equivalent circuit. Although the extrinsic gate drain capacitance could be reduced by the use of a wider recess configuration, it is assumed that the intrinsic drift region is independent of the recess configuration     

Impact of recess-etching-assisting resist-openings on the shapes ofgate grooves for short gate length InAlAs/InGaAs heterojunction FET's

When resist openings are employed to monitor the drain current of InAlAs/InGaAs-heterojunction-based FET's during wet-chemical gate recess, etching rates for InGaAs and InAlAs can be significantly modified by the exposure of the surface metal on the nonalloyed ohmic electrodes to citric-acid-based etchants. Surface metal of Ni enhances the recess etching rate to a degree that is much higher than that in its absence. With nonselective citric acid-based etchant, the presence of Pt surface metal, however, leads to a preferential etching of InGaAs over InAlAs. This behavior of selective etching is attributed to the excess oxidation of InAlAs induced by the high electrode potential of Pt via electrochemical effects. This investigation discloses that the selection of the surface metal that lies beneath the resist openings can be very important if gate recess grooves with desired shapes are to be fabricated     

Enhancement-mode high electron mobility transistors (E-HEMTs)lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (g_mext) of 701 mS/mm and a threshold voltage (V_T) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f _t) of 116 GHz was measured as well as a maximum frequency of oscillation (f_max) of 229 GHz for 0.3 μm gate-length E-HEMTs     

Striped-channel InAlAs/InGaAs HEMTs with shallow-grating structures

Striped-channel (SC) InAlAs/InGaAs HEMTs have been demonstrated with shallow gratings. The shallow grating structure keeps the gate from touching the channel layer and thus solves the gate leakage problem observed in the deep grating devices on InP substrates. Various channel widths have been realized to study the impact of the channel width on the dc and microwave performance. Due to the enhanced charge control in the SC HEMTs, enhanced transconductance/source-drain current (G_m /I_ds) and transconductance/output conductance (G_m /G_ds) were observed. Compared with conventional HEMTs, the SC HEMTs showed degraded f_T due to additional parasitic capacitances and improved f_max due to better carrier confinement     

Comparison Between the Dynamic Performance of Double- and Single-Gate AlInAs/InGaAs HEMTs

The static and dynamic behavior of InAlAs/InGaAs double-gate high-electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2-D Monte Carlo simulator. The model allows us to satisfactorily reproduce the experimental performance of this novel device and to go deeply into its physical behavior. A complete comparison between DG and similar standard HEMTs has been performed, and devices with different gate lengths have been analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. We have confirmed that, for very small gate lengths, short-channel effects are less significant in the DG-HEMTs, leading to a better intrinsic dynamic performance. Moreover, the higher values of the transconductance over drain conductance ratio g_m /g_d, and, especially, the lower gate resistance R_g also provide a significant improvement of the extrinsic f_max.     

Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse

We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (f_t) and slight improvement in power gain cutoff frequency (f_max) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode     

Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications

An 80-nm InP high electron mobility transistor (HEMT) with InAs channel and InGaAs subchannels has been fabricated. The high current gain cutoff frequency (f_t) of 310 GHz and the maximum oscillation frequency (f_max) of 330 GHz were obtained at V_DS = 0.7 V due to the high electron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (f_t) and the corresponding gate delay time caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs composite channel, the impact ionization was not observed until the drain bias reached 0.7 V, and at this bias, the device demonstrated very low gate delay time of 0.63 ps. The high performance of the InAs/InGaAs HEMTs demonstrated in this letter shows great potential for high-speed and very low-power logic applications.     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively     

Physics of breakdown in InAlAs/n+-InGaAs heterostructurefield-effect transistors

InAlAs/n⁺-InGaAs HFET's on InP have demonstrated a high breakdown voltage in spite of the narrow bandgap of the InGaAs channel. In order to understand this unique feature, we have carried out a systematic temperature-dependent study of off-state breakdown. We find that off-state breakdown at room-temperature is drain-gate limited and that the breakdown voltage shows a negative temperature coefficient. Based on these and other findings, we propose that off-state breakdown is a two-step process. First, electrons are injected by thermionic-field emission from the gate to the insulator. Second, electrons enter into the high-field drain-gate region of the channel hot, and relax their energy through impact-ionization. This combined mechanism explains our experimental observations that off-state breakdown in InAlAs/n⁺ -InGaAs HFET's depends both on channel and insulator design. Our findings are relevant to other InAlAs/InGaAs HFET's, such as the MODFET, as well as HFET's based on other narrow-bandgap materials     

Improvement of Impact Ionization Effect and Subthreshold Current in InAlAs/InGaAs Metal–Oxide–Semiconductor Metamorphic HEMT With a Liquid-Phase Oxidized InAlAs as Gate Insulator

The oxidation of InAlAs and its application to InAlAs/InGaAs metal-oxide-semiconductor metamorphic high-electron mobility transistors (MOS-MHEMTs) are demonstrated in this study. After the highly selective gate recessing of InGaAs/InAlAs using citric buffer etchant, the gate dielectric is obtained directly by oxidizing the InAlAs layer in a liquid-phase solution at near room temperature. As compared to its counterpart MHEMT, the fabricated InAlAs/InGaAs MOS-MHEMT exhibits a larger tolerance to gate bias, higher breakdown voltage, lower subthreshold current, improved gate leakage current with the effectively suppressed impact ionization effect, and improved radio-frequency performance. Consequently, the liquid-phase oxidation may also be used to produce gate oxides and as an effective passivation on III-V compound semiconductor devices     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Examination of the kink effect in InAlAs/InGaAs/InP HEMTs using sinusoidal and transient excitation

The kink effect in InAlAs/InGaAs/InP HEMTs is examined in the frequency domain using sinusoidal excitation and in the time domain using voltage pulses applied to the drain of the devices. With the sinusoidal excitation below the kink voltage, two prominent output-resistance frequency-response transitions attributed to traps in the InAlAs or its interfaces were found. These transitions were examined as functions of temperature and yielded trap activation energies near 0.18 and 0.56 eV. Above the kink voltage, a single, broad transition with an activation energy near 0.24 eV was found. Using incremental voltage pulses applied to the drain, a convenient kink signature was obtained. With large voltage pulses which span the kink region, a complex nonexponential transient response was observed due to concurrent capture and emission mechanisms. HEMTs with single- and double-recessed gate structures were found to have similar output resistance dispersion characteristics.<>