A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale

Full-adders are essential parts of digital circuits whereby many arithmetic circuits can be implemented by applying these cells. Therefore speed and power consumption of full-adders affect the performance of digital circuits, FA cell performs a predominant arithmetic operation in them. We utilise carbon nanotube field effect transistors for implementing our proposed designs due to their unique mechanical and electrical properties such as lower delay, lower power consumption, very dense and lower current off. Extensive simulation results using HSpice are reported to demonstrate the acquired significant improvement in performance of FA circuit design in comparison with the state-of-the-art work.     

Leakage power analysis and reduction during behavioral synthesis

This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device-level models for leakage to precharacterize a given register-transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (V/sub T/) technology. The algorithm prioritizes modules giving a high-level synthesis system an indication of where most gains for leakage reduction may be found. We tested our algorithm using a number of benchmarks from various sources. We ran a series of experiments by integrating our algorithm into a low-power high-level synthesis system. In addition to reducing the power consumption due to switching activity, our algorithm provides the high-level synthesis system with the ability to detect and reduce leakage power consumption, hence, further reducing total power consumption. This is shown over a number of technology generations. The trend in these generations indicates that leakage becomes the dominant component of power at smaller feature size and lower supply voltages. Results show that using a dual-V/sub T/ library during high-level synthesis can reduce leakage power by an average of 58% for the different technology generations. Total power can be reduced by an average of 15.0%-45.0% for 0.18-0.07 /spl mu/m technologies, respectively. The contribution of leakage power to overall power consumption ranges from 22.6% to 56.2%. Our approach reduced these values to 11.7%-26.9%.     

Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits

Gate oxide tunneling current (I/sub gate/) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (T/sub ox/) is below 15 /spl Aring/. Increasing the value of T/sub ox/ reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible T/sub ox/ values to each transistor. In this paper, we propose an algorithm for dual-T/sub ox/ assignment to optimize the total leakage power under delay constraints and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T/sub ox/, our approach achieves an average leakage reduction of 86% under 100 nm models and 81% under 70 nm models. We also propose a transistor and pin reordering technique that has minimal layout impact to further reduce the total leakage current up to 12% and I/sub gate/ up to 27% without incurring any delay penalty.     

Reverse-body bias and supply collapse for low effective standby power

Integrated circuits fabricated on a low-leakage process typically display lower performance due to the high threshold voltage (V/sub t/) transistors. Higher performance microprocessors sacrifice power efficiency by decreasing V/sub t/. We show that a processor built on a low V/sub t/ process can achieve the power-per-computation characteristics of one built using a high V/sub t/ process, by using a "drowsy" mode combining reverse body bias (RBB) and voltage collapse when idle. This approach also allows for higher peak performance, if needed. A simple power model is shown to accurately match the measured data; high-operational frequency is demonstrated when in active operation. The circuit techniques used to provide the RBB mode of operation are described and compared with other techniques such as multi-threshold CMOS. While both techniques can be effective for logic, the design effort for RBB is shown to be smaller, while reducing embedded static random access memory standby power without added size.     

A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture

In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an optimal V/sub DD//V/sub t/ operating point that minimizes total active power consumption for different workload and operating conditions. A 175-mV multiply-accumulate test chip using a triple-well technology with tunable supply and body bias values is measured to experimentally verify the tradeoffs between the various sources of power. The test chip shows that there is an optimum V/sub DD//V/sub t/ operating point, although it differs from the theoretical limit because of excessive forward bias currents. Finally, we propose a preliminary automatic supply and body biasing architecture (ASB) that automatically configures a circuit to operate with the lowest possible active power consumption.     

Galois field arithmetic over GF(p/sup m/) for high-speed/low-power error-control applications

This paper presents a very large-scale integration implementation of Galois field arithmetic for high-speed error-control coding applications that is based on the field GF(p/sup m/) with m a small integer such as 2 or 3 and p a prime of sufficient value to generate the required field size. In this case, the Galois field arithmetic operations of addition, multiplication, and inversion are based on architectures using blocks that perform integer arithmetic modulo p. These integer arithmetic operations modulo p have previously been implemented with low delay power products through the use of one hot coding and barrel shifters circuits based on transistor arrays. In this paper, the same one hot coding and barrel shifters circuits are used to construct circuits that implement addition, multiplication, and inversion over GF(p/sup m/). The circuits for GF(p/sup m/) addition and multiplication with p/spl ne/2, achieve a lower power-delay product than designs based on GF(2/sup m/). Also, the architecture for GF(p/sup m/) inversion can be efficiently implemented when m=2 or m=3.     

A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.     

Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

FELERION: a new approach for leakage power reduction

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I/sub off/) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (/spl Delta/V/sub to/) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V/sub t/ mismatch shift. This effect can be so severe that I/sub off/ can increase by more than one order of magnitude with respect to its nominal value due only to V/sub to/ mismatch. We further show through experimental results that the V/sub to/ mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I/sub off/ level as for a V/sub to/ mismatch characterized out of the subthreshold regime.     

Active devices under CMOS I/O pads

Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V/sub t2/, I/sub t2/) of ESD protection devices under various metal level stack structures, shows that i) I/sub t2/ depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V/sub t2/ increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and DC electrical stress by transmission line pulse, as well as AC electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads are independent of bonding pad metal level structures.     

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.     

Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.     

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.     

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.     

Duet: an accurate leakage estimation and optimization tool fordual-Vt circuits

Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V_t processes. The approach is the first to consider the assignment of both the V_t and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device