High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

Low-voltage adders for power-efficient arithmetic circuits

This paper presents the results of a study of alternative adder architectures, a full-swing Bipolar Double Pass-Transistor adder, a new full-swing BiNMOS adder, a reduced-swing Bipolar Double Pass-Transistor adder and a reduced-swing Double Pass-Transistor BiNMOS adder, that outperform a standard CMOS adder up to three times in power-efficiency at supply voltages 1.5–3 V. The Bipolar Double Pass-Transistor adder is more power-efficient than a standard CMOS adder even at a fanout of 1. All remaining proposed adders have a lower crossover capacitance with a standard CMOS adder than the previously reported low-voltage adders. Circuits were designed and fabricated in 0.8 μm BiCMOS technology.     

Leakage effects in metal-connected floating-gate circuits

Floating-gate circuits are useful in many analog applications, although controlling the charge stored on floating gates complicates such circuits. It has been observed that when floating poly gates are connected to metal layers, initial charge is eliminated during fabrication. This Brief presents an alternative to a previously published explanation for this effect. Experiments show that leakage through deposited inter-metal dielectrics is large enough at moderately elevated temperatures to significantly affect circuit operation. Simple modeling suggests that at temperatures typical of back-end integrated circuit processing, leakage would be large enough to rapidly discharge such floating gates.     

Optimal bit-level arithmetic optimisation for high-speed circuits

In terms of speed, the Wallace-tree compressor (i.e. bit-level carry-save addition array) is widely recognised as one of the most effective schemes for implementing arithmetic computations in VLSI design. However, the scheme has been applied only in a rather restrictive way, i.e. for implementing fast multipliers and for generating fixed structures without considering the characteristic of the input signals. The authors address the problem of optimising arithmetic circuits to overcome those limitations. A polynomial time algorithm is presented which generates a delay-optimal carry-save addition structure of an arithmetic circuit with uneven signal arrival profiles. This algorithm has been applied to the optimisation of high-speed digital filters and 5-30% savings have been achieved in the overall filter implementation in comparison to the standard carry-save implementation     

Variable precision arithmetic circuits for FPGA-based multimedia processors

This brief describes new efficient variable precision arithmetic circuits for field programmable gate array (FPGA)-based processors. The proposed circuits can adapt themselves to different data word lengths, avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuits to operate in single instruction multiple data (SIMD) fashion and allows high parallelism levels to be guaranteed when operations on lower precisions are executed. The new SIMD structures have been designed to optimally exploit the resources of a widely used family of SRAM-based FPGAs, but their architectures can be easily adapted to any either SRAM-based or antifuse-based FPGA chips.     

Application of linearly independent arithmetic transform in testingof digital circuits

Recently introduced linearly independent arithmetic (LIA) transforms and their corresponding spectral coefficients are used to detect faults in digital circuits. The results show that for many classes of logical functions, the LIA logic transformations are advantageous in terms of the number of their coefficients that have to be checked to identify the faults when compared to the case of the well-known arithmetic transform     

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.     

BER minimisation via optimal power allocation and eigenbeamforming in MIMO systems

Telecommunication Systems - In this contribution, the convex optimisation technique is deployed to optimize the data transmission in MIMO systems operating via eigenbeamforming. Initially, we study...     

Switched-capacitor power electronics circuits

One of the main orientations in power electronics in the last decade has been the development of switching-mode converters without inductors and transformers. Light weight, small size and high power density are the result of using only switches and capacitors in the power stage of these converters. Thus, they serve as ideal power supplies for mobile electronic systems (e.g. cellular phones, personal digital assistants, and so forth). Switched-capacitor (SC) converters, with their large voltage conversion ratio, promise to be a response to such challenges of the 21st century as high-efficiency converters with low EMI emissions and the ability to realize steep step-down of the voltage (to 3 V or even a smaller supply voltage for integrated circuits) or steep step-up of the voltage for automotive industry or Internet services in the telecom industry. This paper is a tutorial of the main results in SC-converter research and design     

Multiple-valued radix-2 signed-digit arithmetic circuits forhigh-performance VLSI systems

VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit number representations are proposed. A prototype adder chip is implemented with 10-μm CMOS technology to confirm the principle of operation. A multiplication scheme using four-input current-mode wired summations for realizing a high-speed small-size multiplier is presented. The 32×32-b multiplier is composed of 18800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2-μm CMOS technology. It is shown that the technology is also potentially effective for the reduction of the data-bus area in VLSI     

Estimating power dissipation in VLSI circuits

With the shift to low power IC design for personal computing and communication applications, designers' priorities turn to accurate and efficient estimation of power consumption in ICs. Traditional current and power estimation techniques based on a SPICE-like simulation do not provide the necessary efficiency for such an application, and thus new approaches have been recently proposed. In this, the first of a series of articles that reflect the new orientation of this column, Professor Farid Najm of the University of Illinois at Urbana-Champaign presents an overview of different techniques for estimating power consumption in large-scale IC designs. He also discusses computer aided design tools to help in the task     

树电运行低功耗电路

美国华盛顿大学的一组研究人员成功地演示了树木产生的电力足以独立地维持定制电路的运转.这个研究小组并不指望使用树电替代太阳能,但这套系统可以为那些可能被用于检测环境条件或森林火灾的树木传感器提供一种低成本的洗择.     

Minimizing power consumption in digital CMOS circuits

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW     

Integrated reactive components in power electronic circuits

Methods of integrating capacitive and inductive components into new compact devices are presented. Configurations for integrating various combinations of L-C networks are shown. A example of the construction of an integrated L-C for a series-resonant converter is evaluated both practically and experimentally     

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.     

Datapath layout compiler using bit-wise cell-sizing scheme fordelay balancing and power minimisation

While existing datapath compilers generate the same size buffer for all bits, in real datapaths the load capacitance fluctuates according to the bit position, which leads to a nonuniform bit delay with unnecessarily high power consumption. This Letter proposes a datapath layout compiler using a bit-wise cell sizing scheme that reduces the power consumption by equalising the delay of each bit position to the critical bit delay. Experimental results using the example of a real microprocessor have demonstrated a power consumption saving using the tri-state bus of 12% on average, compared to conventional datapaths using a uniform-size cell     

Behavior-mode simulation of power electronic circuits

In this paper, a systematic approach for the behavior-mode simulation of power electronic circuits is presented. To solve the problem of switch-state detection in behavior-mode simulation, a simple-to-implement reinitialization technique is introduced. Furthermore, the issue of time-step selection is discussed. It is illustrated through examples that behavior-mode simulation complements the detailed-mode simulation and enhances the efficiency of the computer-aided analysis and design of power electronic circuits     

Software breadboards for power electronic circuits

A software breadboard is a means of simulating power electronic circuits at the device-level. The objective is to obtain detailed performance information such as device voltage and current waveforms and power dissipations. The intent is to accurately model the circuit for use in place of measurements to assess performance and even in a design mode to pick component values. The issues involved in device level simulation, such as applications, problems, limitations, and advantages, are discussed. An example full bridge power converter is simulated and used for illustration     

Adaptive thyristor power, control circuits

A solid-state circuit is described that provides electronically settable memory control (adaptive control) of thyristor power regulating devices. Electrical power delivered to ac loads, such as lighting, heating, or motors, can be smoothly varied or set to any value from zero to essentially full power by a manual, computer, or remote-controlled application of a voltage pulse to a circuit adapt terminal. Power settings of the circuit can be maintained indefinitely with or without applied power, yet they can be changed quickly (milliseconds) or slowly (dekaseconds) by the application of an appropriate adapt pulse. An adaptive ferroelectric transformer provides the analogue memory capabilities of the control circuit.