一种基于统计的流水线ADC数字后台校准方法

高精度流水线ADC的设计需要校准技术来提高其转换精度.基于统计的数字后台校准方法无需校准信号,直接通过对输出的统计得到误差值的大小,将其从数字输出中移除从而消除了ADC输出非线性.将该校准方法应用于14bit流水线ADC中,仿真结果表明校准后信噪失真比SNR为76.9dB,无杂散动态范围SFDR为73.9dB,有效精度ENOB从9bit提高到12.5bit.     

基于数字自校准的14位SAR ADC的设计

为了降低电容型模数转换器（ADC）中的电容失配带来的非线性影响,提出了一种基于复用低位电容自校准的逐次逼近型（SAR）ADC电路结构,利用低位电容转化高位电容失配引起的误差电压,实现高位电容失配校准。在55 nm CMOS工艺下实现了该ADC结构。该结构ADC工作过程为失调误差提取与正常转换两阶段,失调误差提取阶段中利用低位电容将高位电容失配产生的误差电压转换为误差码并存储,将误差码与正常转化数字码求和得到最终的数字输出,实现电容失配自校准。为了提高ADC采样速率,该结构通过分段结构将电容阵列分为三段降低了单位电容数量。仿真结果表明,在1.2V电源电压,80 MSPS采样速率下,引入电容失配后电路功耗为3.72 m W,有效位数为13.45 bit,信噪失真比（SNDR）为82.75 dB,相比未校准分别提高4.41 bit,26.58 dB。     

一种应用于高精度SAR ADC校准的剪枝神经网络算法

介绍了一种基于剪枝神经网络的后台校准算法,能够对高精度单通道SAR ADC的电容失配、偏移、增益等多个非理想因素同时进行校准,有效提高SAR ADC的精度。本算法不仅可以达到全连接神经网络校准效果,而且同时对贡献小的权重进行剔除,降低了校准电路的资源消耗,加快了神经网络校准算法速度。仿真结果表明,信号频率接近奈奎斯特频率的情况下,对16 bit 5 MS/s的 SAR ADC进行校准,校准后ADC的有效位数从7.4 bit提高到15.6 bit,无杂散动态范围从46.8 dB提高到126.2 dB。     

带输入缓冲电路的12位200兆流水线模数转换器

在12 bit 200 M采样率的模数转换电路(ADC)中实现了片内CMOS输入缓冲电路,输入缓冲电路采用源极跟随器电路构架。通过分析源极跟随器的非线性特点,在输入缓冲电路中加入高通滤波电路、复制电容电路等方式,有效提高了输入缓冲电路的线性度。将该输入缓冲电路用于无数字校准的12 bit 200 M采样率的流水线型模数转换电路(ADC)中,用台积电0.18μm CMOS工艺条件下流片验证,当采样时钟为200 MHz、输入信号频率为10 MHz、振幅为1.4 V_(pp)时其失真噪声比(SNDR)为63.5 dB,无杂散动态范围(SFDR)为78.6 dBc,ADC总体功耗为500 mW。     

基于GaAs HBT工艺的3.8GHz带宽4GS/s 4bit超高速ADC

报道了一种4GS/s 4bit超宽带（UWB）模数转换器（ADC）芯片,采用1.4um发射级宽度、2层金属布线的InGaP/GaAs HBT工艺实现。该芯片采用折叠内插架构来最小化其面积和电路规模。为了消除折叠内插电路中的偶发错误码,该ADC采用了一种新颖的比特同步电路。实测结果表明,其在4GS/s采样率下具有3.8GHz的模拟带宽和2.6GHz的有效精度带宽（ERBW）,在2.6GHz输入带宽内ADC的有效位数大于3.4bit,在4GHz输入带宽内有效位大于3bit。在6.001GHz输入并将输入功率提高4dB后,有效位仍然高达3.49bit,表明该ADC可采样的频率范围包含从第一到第三奈奎斯特区（DC~6GHz）。该芯片的DNL和INL在4GS/s下均小于±0.15LSB,总面积为1.45×1.45 mm2,总功耗为1.98W。     

应用于流水线ADC的LMS自适应校准算法与FPGA实现

研究了应用于流水线模数转换器(ADC)的LMS自适应数字校准算法及其FPGA实现。该校准算法可用于校准大多数已知的误差,包括非线性运算放大器的有限增益、电容失配,以及比较器的失调等。通过Simulink软件,对一个12位160 MS/s的流水线ADC进行建模。采用LMS自适应校准算法对该流水线ADC进行校准,并将算法在Virtex-5上实现了硬件设计。实验结果表明, 输入信号频率为58.63 MHz时,流水线ADC的无杂散动态范围(SFDR)和有效位(ENOB)分别由校准前的46.31 dB和7.32位提高到校准后的82.03 dB和11.12位。     

用于DRFM的4 bit相位量化DAC

设计了一种应用于DRFM系统的4bit相位量化DAC,采用非线性的电流舵结构在标准半导体工艺下实现,芯片面积2.1mm×1.4mm,功耗420mW。测试结果显示该DAC瞬时带宽高于1GHz,与4bit相位量化ADC级联测试时,SFDR在工作带宽内小于-20dBc,性能明显优于3bit相位量化DAC。     

13 bit 50 MS/s CMOS流水线ADC的设计

介绍了一种新的流水线ADC校准算法,并利用该校准算法完成了一个13 bit,50 MS/s流水线ADC的设计.该校准算法对级电路的比较器和后级电路的输出码字的出现频率进行统计,得到各个级电路输出位的真实权值,可以同时校准多种非理想因素如运放有限增益、电容失配等造成的误差.电路采用UMC 0.18μm混合工艺,1.8 V电源电压.通过SPECTRE仿真获得晶体管级级电路的输入输出关系,将其结果导入顶层行为级模型进行校准.仿真结果表明,在50 MHz采样率、5 MHz输入信号下,通过校准算法SFDR由44.1 dB提升至102.2 dB,SNDR由40.9 dB提升至79.9 dB,ENOB由6.5 bit提升至12.98 bit.     

一种时间交叉采样ADC失调与增益误差校准方案

针对时间交叉采样模数转换器的失调、增益误差提出了校准方案.该方案主要通过各通道模数转换器向同一通道校准的方法,首先计算出误差参数,再根据误差参数对数字量进行校准.采用该校准方案对四通道10位640 Msps模数转换器进行校准,经MATlAB仿真,结果表明输入频率为79.14 MHz时,校准后的无杂散动态范围为75.17 dB,信噪比为55.98 dB,有效精度为9.01 bit,比较准前分别提高了24.6 dB、6.47 dB、1.08 bit.     

基于开关运放的低功耗逐次逼近ADC设计

基于UMC 0.18 混合信号工艺,设计了一种低功耗逐次逼近ADC,重点考虑了功耗的优化和电路的改进,采用了开关运放技术,降低了传统缓冲器30%左右的能量消耗,同时比较器低功耗的设计也使该ADC节能的优点更加突出,同时比较器采用了失调校准技术,这样就能够满足10 bit精度的要求.在电源电压1.8 V、采样频率100 kHz的条件下,仿真得到该逐次逼近ADC信噪比为61.66 dB,而静态功耗仅为26μW.该设计的芯片版图面积为1 mm×1mm.     

基于时延滤波的TI ADC采样时间失配校准算法

针对时间交织型模数转换器(TI ADC)子通道间的采样时间失配,提出了一种基于时延滤波的校准算法。该校准算法是一种纯片外校准算法,在片外进行FFT分析并重新拟合理想信号,提取每个子通道信号的时延偏差,再由此偏差计算每个子通道对应的FIR滤波器系数,完成时延偏差的补偿。该校准算法解决了子通道间采样时间失配导致的TI ADC精度不足的问题。将该算法应用于12 GS/s 12 bit ADC交织板。结果表明,无杂散动态范围(SFDR)平均提升了31.356 4 dBc,有效位数(ENOB)平均提升了3.177 6 bit。     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.     

14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration

Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4 and 10.7 , respectively, compared to a 14 bit uncalibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18 um CMOS process occupies an active die area of 4.2 mm² and consumes 140 mW at 1.8 V and 50 MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69 to 0.39 LSB and from 33.60 to 2.76 LSB, respectively.     

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

A 15-b, 5-Msample/s low-spurious CMOS ADC

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-μm CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm², and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing     

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

A 2-GS/s 6-bit self-calibrated flash ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic performance further.The peak DNL and INL are measured as 0.34 and 0.22 LSB,respectively.The SNDR and SFDR have achieved 36.5 and 45.9 dB,respectively,with 1.22 MHz input signal and 2 GS/s.The proposed ADC,including on-chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1...     

A self-calibration method for capacitance mismatch in SAR ADC with split-capacitor DAC

A self-calibration method to calibrate the nonlinearity due to capacitance mismatch in successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It focuses on calibrating the most significant bit (MSB) array in the split-capacitor main DAC (split-MDAC) by using a calibration DAC (CDAC) that contains multiple sub-CDACs. Every bit in MSB array has its corresponding sub-CDAC in CDAC, which enhances the calibration efficiency. To verify the calibration method, a 14 bit, 500 kS/s SAR ADC is implemented, and it is manufactured in 0.35 μm 2P4M CMOS process. The measured results show that the proposed calibration method can assist this SAR ADC to achieve better static and dynamic performance, and its ENOB is improved from 9 bit to 11.98 bit at Nyquist input frequency.