基于TST结构600 V VDMOS终端的设计与优化

以沟槽负斜坡终端(Trench and Slope Termination,TST)结构为研究对象,分析了该结构提高终端表面耐压的原理,利用TCAD软件对该结构进行电性能仿真研究,注意到击穿机制在不同沟槽深度下有所不同。针对两种击穿机制,进行负斜坡倾角优化;最后,从生产角度对TST终端进行优化,以提高其工艺容差。仿真结果表明,经过优化设计的600VTST终端结构,其宽度为127μm,仅为相同耐压水平的场限环场板复合结构终端的50%。提出的设计方法可广泛应用于高压VDMOS的终端设计。     

低压沟槽功率MOSFET导通电阻的最优化设计

研究了低压沟槽功率MOSFET(<100V)在不同耐压下导通电阻最优化设计的差别。给出了确定不同耐压MOSFET参数的方法,简要分析了沟槽MOSFET的导通电阻;利用Sentaurus软件对器件的电性能进行模拟仿真。理论和仿真结果均表明,耐压高的沟槽MOSFET的导通电阻比耐压低的沟槽MOSFET更接近理想导通电阻,并且,最优导通电阻和最优沟槽宽度随着耐压的提高而逐渐增大。     

一种沟槽型SGTMOSFET终端结构

为了在提升终端耐压的同时减少终端的使用面积,基于屏蔽栅沟槽型MOSFET (shielded gate trench MOSFET,简称SGTMOSFET)设计了一种沟槽型终端。通过Sentaurus TCAD软件对终端结构进行仿真,仅改变沟槽和P型环参数,最终使终端的耐压达到了135V,有效终端长度仅为18.5μm。此终端结构适用于中低压领域,且在SGTMOSFET元胞工艺步骤的基础上仅增加了一层掩膜,终端结构工艺和元胞工艺兼容,易于实现。     

高频控制开关用沟槽MOSFET的研究

高频控制开关用功率器件要同时具备极低的导通电阻和栅漏电荷值,从而降低导通损耗和开关损耗.基于器件与工艺模拟软件TsupremⅣ和Medici,研究了工艺参数和设计参数对沟槽MOSFET器件击穿电压、比导通电阻和栅漏电荷的影响,优化设计了耐压30 V的开关用沟槽MOSFET器件.对栅极充电曲线中平台段变倾斜的现象,运用沟道长度调制效应给出了解释.     

高压二极管阻断I-V特性研究

针对高压二极管在终端工艺中出现的3种阻断I-V特性进行了相关测试分析，通过TCAD模拟仿真，结合器件内部电场和漏电流分布，理论研究了3种不同终端负斜角角度对其阻断I-V特性的影响，阐述了导致器件击穿电压降低和软击穿的本质机理。研究结果表明，当终端负斜角θ<1°时，器件获得了低电压的硬击穿特性；当1°≤θ<3°时，器件可获得最佳阻断电压的硬击穿特性。导致硬击穿的本质原因是峰值电场位于有源区边界或靠近边界的位置。对于θ≥3°，高的峰值电场靠近终端区斜角表面边缘而导致I-V呈软击穿特性。     

超结MOSFET功率器件的终端技术分析

为了改善超结MOSFET功率器件的终端击穿特性,提出了一种平面结终端技术,应用柱坐标下的泊松方程证明了这种技术的可行性。提出了超结功率器件终端技术的工艺实现方法并分析了终端结构的电压特性,使用这种超结终端技术仿真得到了一个600V的Coolmos。利用2维仿真软件Medici讨论了终端p柱的数量和宽度因素对击穿电压和表面电场的影响。结果发现,采用变间距的超结结构本身就可以很好地实现超结MOSFET功率器件的终端。     

高压功率MOSFET结终端保护技术及其组合优化设计

场板与场限环是用来提高功率MOSFET抗电压击穿能力的常用结终端保护技术,文章将分别介绍场板与场限环结终端保护技术各自的特点和耐压敏感参数,通过场板和场限环的互补组合来优化设计一款高耐压的VDMOS器件结构,最后采用ATHENA(工艺模拟)和ATLAS(器件模拟)工具来仿真验证优化设计的结果。     

沟槽型MOSFET的发展

在功率变换器中沟槽型MOSFET取代功率二极管传递能量有两个优点：可以用PWM驱动电路灵活地控制MOSFET为不同的负载提供所需的能量;导通电阻低,能耗小。文章介绍了新研究出来的厚栅氧MOSFET,RSOMOSFET,集成肖特基二极管的沟槽型MOSFET,并对它们的机理和性能进行了阐述和分析。     

30 V沟槽MOSFET优化设计

借助半导体专业模拟软件Tsuprem-4 和Medici,模拟得到一组最佳的30 V 沟槽MOSFET结构和工艺参数;给出了特性模拟曲线.在此基础上,详细讨论了沟槽的宽度和深度变化对沟槽 MOSFET的阈值电压、击穿电压、漏电流及导通电阻等特性的影响.最后,根据模拟得到的最佳参数进行了流片实验.结果表明,所设计器件的击穿电压大于35 V,Vgs为10 V下的导通电阻为21 mΩ* mm2.     

超结型高压功率MOSFET结构工作原理

目前,高压功率MOSFET具有平面型和超结型（Super Junction）两种常用的结构。早期,高压功率MOSFET主要是平面型结构,它采用厚的低掺杂的N-的外延层,即epi层,用来保证具有足够的击穿电压,低掺杂的N-的epi层的尺寸越厚,耐压的额定值越大,     

双极RF功率管的深阱结终端

给出了双极 RF功率管新的深阱结终端结构 .模拟分析表明 ,具有优化宽度、优化深度且填充绝缘介质的深阱结终端结构能使雪崩击穿电压提高到理想值的 95 %以上 .实验结果表明 ,深阱结终端结构器件 DCT2 6 0的BVCBO为理想值的 94 % ,比传统终端结构器件高 14 % ;与传统结构相比 ,在不减小散热面积的情况下 ,该结构还减小集电结面积和漏电流 ,器件的截止频率提高 33% ,功率增益提高 1d B     

Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zonejunction termination extension (JTE) have been employed to achieve a high breakdown voltage $(geq!hbox{10} hbox{kV})$ . The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of $hbox{1.1} times hbox{10}^{13} hbox{cm}^{-2}$ has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.      

A novel trench termination design for 100-V TMBS diode application

In this letter, a novel trench termination structure that can inhibit the reverse leakage current substantially and reduce the process cost is introduced. For trench type power devices, such as trench MOS barrier Schottky (TMBS) diodes, this new termination structure can be processed simultaneously with the active region without any additional mask. Simulation and experimental results show that TMBS diodes with this new termination structure can achieve a reverse blocking voltage of 100 V with a leakage current density as low as 8.4×10^-4 A/cm²     

一种沟槽-场限环复合终端结构的设计

为了改善硅功率器件击穿电压性能以及改善IGBT电流的流动方向,提出了一种沟槽-场限环复合终端结构。分别在主结处引入浮空多晶硅沟槽,在场限环的左侧引入带介质的沟槽,沟槽右侧与场限环左侧横向扩展界面刚好交接。结果表明,这一结构改善了IGBT主结电流丝分布,将一部分电流路径改为纵向流动,改变了碰撞电离路径,在提高主结电势的同时也提高器件终端结构的可靠性;带介质槽的场限环结构进一步缩短了终端长度,其横纵耗尽比为3.79,较传统设计的场限环结构横纵耗尽比减少了1.48%,硅片利用率提高,进而减小芯片面积,节约制造成本。此方法在场限环终端设计中非常有效。     

Maximum surface and bulk electric fields at breakdown for planar and beveled devices

Techniques previously presented for predicting breakdown voltage on planar devices with and without a field ring and in negative beveled devices are greatly extended so that the peak bulk and surface electric fields at breakdown can now be predicted. In addition, new techniques are described which for the first time allow the peak bulk and surface electric fields to be predicted for all positive and double positive beveled devices. Using this paper it becomes possible to predict peak bulk and surface electric fields as well as breakdown voltage for all planar and beveled devices. This is accomplished by the use or normalization procedures which allow dependencies on the substrate doping, junction depth, surface concentration, junction curvature, and bevel angle to be reduced to a single dependence. It is shown that the positive bevel is most effective in reducing surface electric fields with the negative bevel, double positive bevel, and the field ring for planar devices in decreasing order of effectiveness.     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

Robust PIN photodiode with a guard ring protection structure

A guard ring (GR) structure is used to protect a planar InGaAs pin photodiode. The human body model (HBM) measurement results show that a photodiode with a GR, which is shorted to the cathode, is able to withstand an electrostatic discharge (ESD) threshold voltage of up to 200 V, whereas a similar photodiode without a GR structure can only withstand 50 V ESD threshold voltage. The capacitance and bandwidth measurement results show that the GR has negligible negative effects on the pin diode performance.     

Double positive beveling: A better edge contour for high-voltage devices

A theoretical analysis is made of the field distribution near the surface of p-n-p structures with double positive edge geometry. This geometry offers in principle the possibility of avoiding the limitations and disadvantages inherent in the use of negative bevel angles. The results show that the reduction of the maximum field at the surface is not as easy as for the case of a simple positive bevel angle and that consequently the passivation of the surface may present more problems. Nevertheless, it is demonstrated that this geometry offers a number of great advantages and presents a real alternative for use in future high-voltage devices. A number of devices, dimensioned for a breakdown voltage of 6 kV, were made with this edge geometry. The measurements show that the reverse current corresponds to the thermally generated current in the space-charge layer and that no significant current flows at the surface. The breakdown voltage corresponds to the theoretical breakdown voltage in the bulk, unlike in the case of double negative beveling. The advantages of this geometry with respect to the conventional negative bevel angle are no significant reduction of active area, no dependence on the doping profile, and no limitation in voltage. A disadvantage, however, is the presence of higher fields at the surface.     

3300V沟槽栅IGBT的衬底材料的优化设计

使用TCAD仿真软件对3 300 V沟槽栅IGBT的静态特性进行了仿真设计.重点研究了衬底材料参数、沟槽结构对器件击穿电压、电场峰值等参数的影响.仿真结果表明,随衬底电阻率增加,击穿电压增加,饱和电压和拐角位置电场峰值无明显变化;随衬底厚度增加,击穿电压增加,饱和电压增加,拐角位置电场峰值降低;随沟槽宽度增加,饱和电压降低,击穿电压和拐角位置电场峰值无明显变化;随沟槽深度增加,饱和电压降低,击穿电压无明显变化,拐角位置电场峰值增加;随沟槽拐角位置半径增加,击穿电压和饱和电压无明显变化,但拐角位置电场峰值减小.选择合适的衬底材料对仿真结果进行实验验证,实验结果与仿真结果相符,制备的IGBT芯片击穿电压为4 128 V,饱和电压约为2.18 V.     

Electric fields at and near the surface of p-n junctions with negative bevel angles

A new investigation of the field distribution at and near the surface of p-n junctions with negative bevel angles has shown that an absolute field maximum exists 20?40 ?m below the surface. This field maximum is reduced with smaller bevel angles, but is stronger for structures with a higher breakdown voltage in the bulk.