High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model     

Bipolar stressing, breakdown, and trap generation in thin siliconoxides

Thin silicon oxide films were stressed with bipolar pulses in which the magnitudes of both the positive and negative pulses were independently varied, The time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxides during the stresses were measured and compared with oxides that had been stressed with unipolar pulses or stressed with constant dc voltages. For the bipolar stresses it was found that the time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxide all increased as the magnitude of the opposite polarity, nonstressing pulse was increased, until the opposite polarity pulse became large enough to become the stressing pulse. The time-to-breakdown reached a maximum when the magnitude of the stressing pulse was approximately 1 V larger than the magnitude of the nonstressing pulse. The model that was used to explain these increases involved generation of traps inside of the oxide and the lack of spatial correlation between the traps generated by injection from one interface with the traps generated by injection from the other interface     

Improved transconductance under high normal field MOSFETs withultrathin nitrided oxides

The gate-voltage dependence of electron mobility at 298 and 82 K in MOSFETs with nanometer-range thin (reoxidized) nitrided oxides prepared by rapid thermal processing (RTP) at 900-1150°C for 15-300 s is discussed. Rapid nitridation improves the mobility and current derivability under high normal field over thermally grown oxides at both temperatures: the transconductance g_m at a gate drive of 3.5 V is improved by half an order of magnitude, whereas the peak g_m remains comparable to that of an oxide. Nitridation also avoids the negative g_m observed at 82 K for an oxide MOSFET. These improvements are substantially unchanged by additional reoxidations     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Neutral electron trap generation under irradiation in reoxidizednitrided gate dielectrics

In this study we report for the first time results on neutral electron trap generation in reoxidised nitrided oxide dielectrics under various radiation doses and bias conditions and compare the results with the conventional oxides. We see very little electron trap creation in RNO dielectrics for radiation doses up to 5 Mrad (Si) and for bias fields up to ±2.5 MV/cm. We explain our results in RNO and oxide dielectrics using a three step defect creation model     

SILC as a measure of trap generation and predictor ofTBD in ultrathin oxides

The theoretical basis of stress-induced leakage current (SILC) as a measure of bulk trap density within thin oxide films is explored. Contrary to popular belief, this measure is neither absolute, nor do most papers in the literature sufficiently specify the measurement conditions to make their comparison meaningful. We also explore the relationship between SILC generation rate and the time-to-breakdown, and show that only a very specific definition of SILC generation can capture the voltage dependence of the time-to-breakdown     

Interface trap generation by FN injection under dynamic oxide fieldstress

Interface trap generation under dynamic (bipolar and unipolar) and dc oxide field stress has been investigated with the charge pumping technique. It is observed that regardless of stress type, whether dc or dynamic (bipolar or unipolar), and the polarity of stress voltage, interface trap generation starts to occur at the voltage at which Fowler-Nordheim (FN) tunneling through the oxide starts to build up. For positive voltage, interface trap generation is attributed to the recombination of trapped holes with electrons and to the bond breaking by the hydrogen (H and H⁺) released during stressing. For negative voltage, in addition to these two mechanisms, the bond breaking by energetic electrons may also contribute to interface trap generation. The frequency dependence of interface trap generation is also investigated. Interface trap generation is independent of stressing frequency for unipolar stress but it shows a frequency dependence for bipolar stress     

A study of interface trap generation by Fowler-Nordheim andsubstrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO₂ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D _it) generation due to hot holes under V_G<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D_it) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D_it) than SHH stress. It is also observed that N₂O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O₂-grown oxide. N₂O-grown gate oxide is shown to have less SHH stress-induced interface traps than O₂-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices     

Charge generation in TRAPATT diodes

The charge generated during an avalanche in a TRAPATT diode is shown to be proportional to the current at the instant of triggering. The constant-current frequency is shown to be an important diode parameter.     

Hot-carrier-induced degradation in reoxidized-nitrided-oxiden-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO₂ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing     

Thermal gradient in solder joints under electrical-current stressing

The thermal gradient and temperature increase in SnAg3.5 solder joints under electrical-current stressing have been investigated by thermal infrared microscopy. Both positive and negative thermal gradients were observed under different stressing conditions. The magnitude of the thermal gradient increases with the applied current. The measured thermal gradients reached 365°C/cm as powered by 0.59 A, yet no obvious thermal gradient was observed when the joints were powered less than 0.25 A. The temperature increase caused by joule heating was as high as 54.5°C when powered by 0.59 A, yet only 3.7°C when stressed by 0.19 A. The location of heat generation and path of heat dissipation are believed to play crucial roles in the thermal gradient. When the major heat source is the Al trace, the thermal gradient in the solder bumps is positive; but it may become negative because the heat generated in the solder itself is more prominent.     

The effect of hydrogen on trap generation, positive chargetrapping, and time-dependent dielectric breakdown of gate oxides

The effect of high-temperature (≈900°C) hydrogen on the gate oxides of MOS devices is studied. Hydrogen is introduced into devices by either high-temperature anneal or conventional process steps such as low-pressure chemical vapor deposition (LPCVD) of Si₃N₄. In all cases, measurements of high-field stress behavior show that high-temperature hydrogen steps reduce time to breakdown and increase bulk and interface trap generation, but do not affect the generation of positive charge. These results indicate that the wear-out mechanism of gate oxides at high fields is related to trap generation rather than to accumulation of positive charge     

Defect generation statistics in thin gate oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.     

Donor-like interface trap generation in pMOSFET's at roomtemperature

The generation of donor-like interface traps under room temperature bias stress is observed. This generation process is insensitive to the gate polarity, hot carrier stress, and positive charge formation in the gate oxide. It requires the simultaneous presence of boron- and water-related species. The generated interface traps are nonuniformly distributed along the channel     

Sinusoidal AC stressing of thin-gate oxides and oxide/siliconinterfaces in 0.5-μm n-MOSFETs

Sinusoidal ac signals are applied to 90-Å thick gate-oxide in 0.5-μm n-MOSFETs. The objective is to emulate ac stressing to devices, recently reported to occur during plasma processes. AC stressing is found to be more damaging to the oxide and oxide/silicon interface when compared to dc stressing. The damage induced by the ac stress is observed to depend on the signals frequency and amplitude. It is proposed that carrier hopping is primarily responsible for oxide current and device damage observed following the ac stress. This hopping current is insignificant during high-field dc stress when Fowler-Nordheim tunneling becomes the dominant conduction mechanism     

Correlation of stress-induced leakage current in thin oxides withtrap generation inside the oxides

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission     

超短脉冲强激光场高次谐波的历史回顾与展望

总结了近几年来超短脉冲强激光场高次谐波实验及理论方面的工作，讨论了高次谐波的重要意义及可能应用，展望了强场谐波理论及实验方面进展及可行性方案。     

Charge transport in poly(p-phenylene vinylene) at low temperature and high electric field

Charge transport in poly(2-methoxy, 5-(2′-ethyl-hexyloxy)-p-phenylene vinylene) (MEH-PPV)-based hole-only diodes is investigated at high electric fields and low temperatures using a novel diode architecture. Charge carrier densities that are in the range of those in a field-effect transistor are achieved, bridging the gap in the mobility versus charge carrier density plot between polymer-based light-emitting diodes and field-effect transistors. The extended field range that is accessed allows us to discuss the applicability of current theoretical models of charge transport, using numerical simulations. Finally, within a simple approximation, we extract the hopping length for holes in MEH-PPV directly from the experimental data at high fields, and we derive a value of 1.0 ± 0.1 nm.     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%