Drain current dlts analysis of recoverable and permanent degradation effects in AlGaAs/GaAs AND AlGaAs/InGaAs HEMT'S

We present a detailed study of drain current DLTS spectra performed on asreceived and failed AlGaAs/GaAs and AlGaAs/InGaAs HEMT's of four different suppliers submitted to hot-electron tests. We demonstrate that a remarkable correlation exists between DLTS features and permanent and recoverable degradation effects. In particular, different behaviours have been found: (i) recoverable effects seems to be correlated with modulation of charge trapped on DX and ME6 centers. (ii) permanent degradation consisting in a decrease in Id and V_T is due to negative charge trapping and is associated with a large increase of a peak having Ea=1.22 eV in the DLTS spectra of failed devices; (iii) development of traps in the gate-to-drain access region induces a permanent increase in drain parasitic resistance Rd and decrease in Id, and is correlated with the growth of a “hole-like” peak in DLTS spectra measured after hot-electron tests.     

The impact of static and dynamic degradation on SOI “smart-cut” floating body MOSFETs

The impact of static (DC) and dynamic (AC) degradation on SOI “smart-cut” floating body MOSFETs, was investigated by means of deep level transient spectroscopy (DLTS). The study was based on drain current signal recording, immediately after the transistor transition from OFF- to ON-state. In order to isolate the activity of capture/emission carrier mechanisms, undesirable parasitic effects such as drain current overshoot were suppressed by appropriately biasing the transistor substrates. Under DC degradation regime, DLTS spectra disclosed that carrier capture/emission process occurred through discrete traps governed by thermally activated mechanisms. Furthermore, polarization phenomena emerged. Under AC degradation regime, although the existence of interface states in Si-SiO2 interface was dominant, the revelation of shallow traps in low temperature domain was also monitored.     

Modeling the effects of surface states on DLTS spectra of GaAsMESFETs

A resistance deep-level transient spectroscopy (DLTS) model which explains the effects of surface states on DLTS spectra of GaAs MESFETs is presented. The model includes both deep traps in the active channel under the gated region and the surface states on the ungated surface between the contacts of gate and source as well as gate and drain. Surface states are shown to result in minority holelike DLTS signals. The model reveals that the surface-state energy levels can be reliably determined from these holelike DLTS signals, although the concentrations cannot be accurately profiled due to the strong dependence of the peak magnitude of the holelike signals on the ungated surface conditions, in particular, the surface leakage current. The peak magnitude of the holelike signals are shown to depend strongly on the filling pulsewidth t_p used in a DLTS measurement. It is also shown that the peak magnitude decreases rapidly as the ratio of the gate length to the gate-source spacing is increased. It is expected that the model can be a useful tool for investigating the passivation effects of the ungated surface on a short-gate GaAs MESFET     

Effect of surface passivation of AlGaN/GaN heterostructurefield-effect transistor

The effect of SiN passivation of the surface of AlGaN/GaN transistors is reported. Current deep level transient spectroscopy (DLTS) measurements were performed on the device before and after the passivation by a SiN film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device. The DLTS spectrum obtained from the measurement of the passivated device showed a significantly lower peak for this trap. The discrepancy in the DLTS peak amplitude is explained by the effect of the passivation on the surface traps and underlines the surface nature of the major defect noticed in the device     

Comparative study of admittance spectroscopy and DLTS in determining trap levels of CdTe-ZnTe heterojunctions

A study of deep levels in the depletion region of an n⁺-CdTe-p-ZnTe heterojunction has been made using admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS) methods. Four trap level signals were observed by both As and DLTS methods. Activation energies, trap densities and capture cross sections of the shallowest and the deepest trap levels of 0.12 and 1.0 eV, determined from AS data, agree well with DLTS results. These are identified as hole traps by DLTS. A reasonable agreement is also found in case of the electron trap level at 0.24 eV. The trap level with an activation energy of 0.58 eV observed from AS has been shown to be a hole type and exhibits a complex behavior in DLTS. The mechanism of the 0.58 eV trap level is discussed in this paper.     

Correlation between trap characterisation by low frequency noise, mutual conductance dispersion, oscillations and DLTS in GaAs MESFETs

The characteristics of traps observed by excess generation-recombination (g-r) noise spectroscopy, g_M-frequency dispersion spectroscopy and low frequency oscillations are correlated with the properties observed by different versions of DLTS experiments applied to GaAs MESFETs. A comparison of the trap parameters reveals the relative sensitivities of the techniques and any systematic differences. The DLTS experiments have located the positions of the traps so that the bias dependence of the trap parameters for each technique should allow any unknown trap also to be located within the device structure.     

Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

The paper presents results of study of threshold voltage (V_T) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced V_T degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. “Direct” and “reverse” antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.     

Surface influence on the conductance DLTS spectra of GaAs MESFET's

The observation of hole traps in small-signal GaAs MESFET's has been extensively reported in the literature. Previously these have been attributed to trapping at the active layer-substrate interface. Evidence is presented here, based on conductance DLTS and low-field low-frequency transconductance dispersion measurements on MESFET's of various geometries, to suggest that the main contribution to the "hole trap-like" spectrum in conductance DLTS is not bulk hole traps. Instead we believe that this phenomenon arises from changes in the population of surface states in the ungated access regions of the device, resulting in modulation of the surface depletion layer in series with the gate depletion region.     

An efficient technique for analyzing deep level transient spectroscopy data

A novel Deep Level Transient Spectroscopy (DLTS) method is introduced. The technique uses two data points taken from a DLTS capacitive transient to make a direct calcu-lation for the emission rate. The method is valid for all points of a thermal scan, as opposed to Lang’s original DLTS, which can only calculate the emission rate at the DLTS peaks. A complete Arrhenius plot can be constructed using one to four temper-ature scans. The method is additionally applied to simulated noise. Electron traps in Silicon are investigated with the new technique, using laboratory data. A comparison is made between this new method, the original DLTS of Lang, and recent developments made by other authors.     

The influence of inhomogeneous trap distribution on results of DLTS study

A model is developed to describe how a narrow distribution of deep traps adjacent to quantum dots (QDs) influences the trap-related signals measured by frequency scanned deep level transient spectroscopy (FS-DLTS). By comparison with experiment, it is demonstrated that traps with a steep concentration gradient, positioned in the so called transition layer close to the edge of the depletion region (“λ-effect”), have a strong influence on DLTS signal amplitudes. This is manifested by an extreme sensitivity to the change in the Fermi-level position when temperature is varied.     

Fourier-transformation analysis of deep level transient signals in semiconductors

A new processing method for DLTS characterization is proposed through an analysis by means of Fourier transformations. Emission time constants for one or two traps at a given temperature can be obtained from an analysis of the Fourier spectrum of the isothermal-capacitance transient signal without any determination of spectral peak positions. Thus it is easy to automate DLTS measurements and signal processing with this analysis. This method is also advantageous in judging whether a measured signal includes single or plural traps.     

Reliability of networks of three-state devices

A three-state device is a device that can exhibit two different types of failure mode, an “open” failure and a “shorted” failure. This paper treats networks whose arcs may experience these two failure modes in addition to the normal “success” state. The network is undirected and has two designated nodes as source and sink. Such a network is itself subject to each of the two failure modes, and the reliability problem considered is computation of the probability of each of the three states of the network. Our observation is that such problems are easily reduced to the usual two-state network reliability problem for which common techniques such as the factoring theorem are readily applicable.     

Electrical passivation by hydrogen plasma treatment of transition metal impurities in germanium

Transition metal impurities in germanium introduce deep levels in the band gap, which may influence the lifetime of carriers and leakage currents of devices. In this work it is shown that Ti, Cr and Fe centres in germanium can be passivated using plasma hydrogenation. The metals have been implanted at 90 keV in n- and p-type wafers and in-diffused during a 5 min thermal anneal at 500 °C. Samples have been hydrogenated using a DC plasma for 4 h at 200 °C and Schottky diodes were made for measurement using DLTS. It is found that the levels of metal impurities are passivated by hydrogenation. Characteristic hole and electron traps are assigned to the irradiation damage induced by the direct plasma exposure. Metal-specific levels are tentatively assigned to transition metal–hydrogen-related centres. Two hole traps at 0.05 and 0.10 eV above the valence band are only present in the Cr-doped samples and are tentatively assigned to chromium–hydrogen complexes. A comparison is made with copper–hydrogen in germanium.     

Quantifying charging damage in gate oxides of antenna structures for WLR monitoring

A new method to quantify the reliability risk for gate oxide with plasma induced charging damage (PID) is established. Based on existing antenna test methodology the quantity of inflicted damage is expressed in a physical meaningful number by means of a simple model applicable for thick oxides (>5 nm).This model takes trap activation, trap filling, detrapping and also traps generation under constant current test condition (“revealing stress”, “diagnostic stress”) into account. For the corresponding development of the measurable external supply voltage with time an equation is derived. Experimental test data from different oxide thicknesses are fitted to this model equation to obtain its main parameters, the cross section values. These cross section values describe the probabilities for the different trap/detrap processes during stress. Cross section values thus found extend published data for lower electric fields to high electric fields necessary for a fast test.The number of plasma induced traps, which was added to the oxide during wafer processing, can now be determined by applying an electron trapping rate (ETR) test method, and combining it with our dynamic trap generation/filling model. The obtained number of PID related traps opens a path to calculate the corresponding reduction of oxide lifetime. Real measurement data are used to illustrate the method and its applicability to fast wafer level reliability (fWLR) monitoring.     

用深能级瞬态谱法测量GaAS MESFET中的深能级

本文介绍了用深能级瞬态谱(DLTS)法测量GaAs MESFET的深能级杂质和缺陷。在有源层中一般没有测到深能级杂质和缺陷,但在有源层与缓冲层界面附近测到了多个空穴陷阱和电子陷阱。其中空穴陷阱的能级有0.41eV、0.53eV、0.68eV、0.91eV;电子陷阱的能级有0.30eV、0.44eV、0.84eV。并对部分陷阱的性质作了初步的讨论。     

Effects of GaAs buffer layer and lattice-matching on deep levels in Zn(S)Se/GaAs heterostructures

The effects of GaAs buffer layer and lattice-matching on the nature of deep levels involved in Zn(S)Se/GaAs heterostructures are investigated by means of deeplevel transient spectroscopy (DLTS). The heterojunction diodes (HDs) where nZn(S)Se is grown on p⁺-GaAs by metalorganic vapor phase epitaxy are used as a test structure. The DLTS measurement reveals that when ZnSe is directly grown on a GaAs substrate, there exist five electron traps A-E at activation energies of 0.20, 0.23, 0.25, 0.37, and 0.53 eV, respectively. Either GaAs buffer layer and lattice-matching may reduce the incorporation of traps C, D, and E, implying that these traps are ascribed to surface treatment of GaAs substrate and to lattice relaxation. Concentration of trap B, which is the most dominant level, is proportional to the donor concentration. However, in the ZnSSe/GaAs sub. HD, another trap level, instead of trap B, locates at the almost same position as that of trap B, and it shows anomalous behavior that the DLTS peak amplitude changes drastically as changing the rate windows. This is explained by the defect generation through the interaction between sulfide and a GaAs substrate surface. For the trap A, the concentration is a function of donor concentration and lattice mismatch, and the origin is attributed to a complex of donor induced defects and dislocations.     

Digital deep level transient spectroscopy considered for discrimination of traps closely spaced in emission coefficients in semiconductors

A method is presented for analysis of digitally recorded capacitance transients to give activation energies and capture cross-sections of two deep levels which would yield overlapping peaks in conventional DLTS spectra. It is shown that baseline errors can be overcome by proper analysis of the data. The accuracy of the method is examined by simulation with parameters representative of a typical DLTS system. The addition of various noise levels is also simulated and the effects of averaging of transients on the ability to discriminate closely spaced traps is examined quantitatively.     

Giant traps on the surface of hydride vapor phase epitaxy-grown free-standing GaN

Extended defects on the top surface of a 250-μm-thick free-standing GaN sample, grown by hydride vapor phase epitaxy (HVPE), were studied by deep level transient spectroscopy (DLTS) and scanning surface potential microscopy (SSPM). For comparison, similar studies were carried out on as-grown HVPE-GaN samples. In addition to the commonly observed traps in as-grown HVPE-GaN, the DLTS measurements on free-standing GaN reveal a very high concentration of deep traps (∼1.0 eV) within about 300 nm of the surface. These traps show nonexponential capture kinetics, reminiscent of those associated with large defects, that can accumulate multiple charges. The SSPM measurements clearly reveal the presence of charged microcracks on the top surface of the sample. It appears that the “giant traps” may be associated with these microcracks, but we cannot rule out the involvement of other extended defects associated with the near-surface damage caused by the polishing/etching procedure.     

Electron traps created by high temperature annealing in MBE n-GaAs

An electron trap with a thermal activation energy of 0.83 eV from the conduction band is common in the deep level transient spectroscopy (DLTS) spectra of vapor phase epitaxial (VPE) n-GaAs, but is not observed in the DLTS spectra of as-grown molecular beam epitaxial (MBE) n-GaAs. We show here that this trap is created during high temperature annealing of MBE samples with a Si₃N₄, encapsulant. The trap concentration is correlated with the annealing temperature and time, suggesting the outdiffusion of a constituent atom resulting in the formation of a vacancy or vacancy-complex. Other electron traps observed in the DLTS spectra of asgrown MBE n-GaAs are annealed out for temperatures at or above 800° C.     

A DLTS study of deep levels in the band gap of textured stoichiometric p-CdTe polycrystals

Deep-level transient spectroscopy (DLTS) was used to identify a set of deep electronic states in the band gap of textured p-CdTe polycrystals whose composition was almost stoichiometric. Four hole traps and two electron traps were observed. It is shown that the deepest hole trap with a level at E _v+0.86 eV corresponds to a prevalent defect in this material. Special features of the line shape in the DLTS spectrum and the logarithmic dependence of population of this level on the duration of the filling pulse correspond to an extended defect related most probably to dislocations at the grain boundaries.