Electromigration of silicon and phosphorus in tantalum polycide interconnections

TaSi2/n⁺-poly-Si interconnections of integrated circuits were investigated after high direct current density stress at elevated temperatures. The current density was increased up to values that caused failures of the interconnections due to electromigration. We found in our experiments that material migrated from the anode to the cathode causing open-circuit failure at the anode region. At the cathode, the material piled up forming hillocks. Material depletion and accumulation are caused by positive or negative mass flow divergences due to temperature gradients near the pads. The accumulated material at the cathode was analyzed by high-resolution Auger and SIMS spectroscopy. The obtained spectra show only silicon and phosphorus peaks with an increased phosphorus concentration at the cathode area. Hence, it can be concluded that in TaSi2/n⁺-poly-Si interconnection mainly material of the polysilicon layer including the dopant phosphorus is moved by electromigration. In contrast to these results of dc experiments, no electromigration occurred during equivalent ac stress.     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Si-gate CMOS devices on a Si/CaF2/Si structure

Si-gate CMOS inverter chains and 1/8 dynamic frequency dividers have been fabricated on a Si/CaF2/Si structure. A high-quality heteroepitaxial Si/CaF2/Si structure was formed by successive molecular-beam epitaxy of CaF2and Si. Transistors have been fabricated with an improved CMOS process that prevents crystal degradation during the fabrication process as much as possible. The maximum effective mobilities are about 570 and 240 cm²/V . s for n-channel and p-channel transistors, respectively. The inverter chain with an effective channel length of 2.0 µm has a delay time per gate of 360 ps. A maximum operating frequency of 300 MHz is obtained in the divider with an effective channel length of 2.5µm at a supply voltage of 5 V. These results indicate that the Si/CaF2/Si structure has potential for the fabrication of high-speed silicon-on-insulator devices.     

MOS Compatibility of high-conductivity TaSi2/n+poly-Si gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi2/2.5 kÅ poly-Si, which was sintered prior to patterning with a CF4/O2plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-Å SiO2, As-implanted source/ drain), VTand β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n⁺poly-Si gates. Static and dynamic bias-temperature aging stability of the VFBis excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.     

γ—Radiation effects on MOSFET's fabricated with NMOS Submicrometer technology

In this letter, we report γ-radiation effects on MOSFET's fabricated with NMOS submicrometer technology. We have investigated the radiation sensitivity of n-channel MOSFET's with Leffvarying from 6 to 0.3 µm and with a gate oxide thickness of 250 Å. We observed that, for radiation doses ≤ 10⁴rad's, the threshold voltage shift is less than 75 mV and this shift is independent of the device geometry (even for Leff= 0.3 µm). A comparision has also been made between TaSi2gate MOSFET's and poly-gate MOSFET's. The deposition of TaSi2on poly/oxide/silicon structure does not decrease the radiation sensitivity of these MOSFET's. We have also compared MOSFET's fabricated with X-ray lithography and optical lithography. The X-ray lithography does not have a significant effect on the radiation sensitivity of these MOSFET's.     

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (IL)which vary from wafer to wafer, typicaily from 10^-11to 10^-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10^-11∼ 10^-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al2O3-Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of IL, which support the general conclusions of the model, are presented. ILis shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of ILis the state of the Al2O3-Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10^-9A/mil of gate width.     

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n⁺source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

Dominant subthreshold conduction paths in short-channel MOSFET's

Conduction modes in off-biased n⁺-polysilicon gate MOSFET's of both polarities have been analyzed by two-dimensional device simulations. It was found that the dominant leakage paths in p-channel and n-channel enhancement devices occur in the bulk and at the surface, respectively, atV_{GS} = V_{BS} = 0. The control of these two distinct modes is the flatband voltage of the gate. The situation is exactly reversed when boron-doped polysilicon is used as the gate. Additionally, we showed that this physical insight can be readily gained by a quasi-two-dimensional analysis of the surface potential and its bending into the substrate. The leakage mode in short-channel MOSFET's with other gate material or with different interface properties generated by radiation or other stresses can thus be easily assessed. Subthreshold characteristics have been simulated for n⁺-polysilicon-gate low-threshold p-channel transistors having a p-type surface from boron counterdoping. The computed channel-length dependence is found to be in good agreement with measured data. Dominant leakage paths, in this case, remain in the bulk, while the surface holes from boron counterdoping are depleted by the flatband voltage. Since the common practice for reducing subthreshold leakage is to enhance substrate impurity concentration where punchthrough occurs, we therefore conclude that different strategies of process tailoring are required for MOSFET's of different gate material, surface polarity, and interface properties.     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained     

Device design for the submicrometer p-channel FET with n+polysilicon gate

CMOS has become one of the most important technologies for VLSI applications. If the conventional n⁺polysilicon gate approach is to be maintained for VLSI CMOS, the p-channel transistor will cause problems in scaling down to submicrometers due to the counter-doping that is necessary to adjust the threshold voltage to a reasonable value. The depth of the p⁺source-drain junctions will also cause short-channel effects. This paper presents in-depth analysis of the submicrometer p-channel transistor structure. The effects of the counter-doping junction depth and the source-drain junction depth on the device subthreshold characteristics are discussed. Criteria for the submicrometer p-channel transistor structure with good subthreshold characteristics are presented. A new technique for minimizing the counter-doping junction depth is also presented. Submicrometer p-channel transistors with n⁺polysilicon gate were fabricated using this new technique as well as techniques for forming very shallow p⁺-junctions. Devices with submicrometer channel lengths showed very good subthreshold characteristics, as predicted by simulations.     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.     

p-Channel TFT's using magnetron-sputtered Ta2O5films as gate insulators

Metal-gate thin-film transistors (TFT's) have been fabricated in layers of laser-recrystallized polycrystalline silicon on fused quartz substrates at processing temperatures below 625°C. Tantalum pentoxide (Ta2O5) was used as a gate insulator instead of a conventional thermally grown silicon dioxide (SiO2). Ta2O5gate insulator was deposited onto the recrystallized silicon layer at room temperature, using an RF-magnetron sputtering system. The reactive ion etching method, using CF4as a reactive gas, was employed in patterning deposited Ta2O5. These TFT's have exhibited p-channel depletion-mode characteristics with a threshold voltage of 2.5 V and a transconductance of 70 µS at Vg= - 2 V. An on-off current ratio exceeding 10⁵has been obtained.     

A compatible NMOS, CMOS metal gate process

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V^-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.