Innovative wire bonding method using a chemically reacted thin layer for chips with copper interconnects

This paper presents a novel method in which an oxide film is used to facilitate the thermosonic wire bonding of gold wire onto copper pads. A cuprous oxide film is generated by controlling the pH values of the chemical solution. Compared to cupric oxide films, the cuprous oxide film is denser and more brittle and therefore facilitates the bonding process without the need for the elaborate procedures and equipment required by more conventional wire bonding methods.     

铜互连线静水应力的有限元模拟

本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。     

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress,which is critical to the formation of stress-induced voiding(SIV) in copper damascene interconnects.Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry.In addition,hydrostatic stress is studied through the influences of different low-k dielectrics,barrier layers and line widths of copper lines,and the results indicate that hydrostatic stress is strongly dependent on these factors.Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.     

Effect of stresses on the evolution of annealing textures in Cu and Al interconnects

A new model is advanced to account for the evolution of annealing textures in copper and aluminum interconnects based on strain and surface energies. The interconnects, whether they are conventionally or damascene-process fabricated, are subjected to stresses during room temperature or elevated temperature annealing, which, in turn, gives rise to strain energies. The strain energy of a deposit is influenced by its texture and geometry. The annealing texture of an interconnect line is determined such that its elastic strain and surface energies are minimal. The measured textures in damascene-processed copper interconnects and a published result of conventionally processed Al-1%Cu interconnects are discussed based on minimization of their strain and surface energies.     

Three-dimensional simulation of microstructure evolution in damascene interconnects: Effect of overburden thickness

Microstructure in the damascene interconnects evolves with the overburden layer, an excessive metal layer over trenches. We present the results of three-dimensional simulation, which show the effects of overburden thickness on microstructure evolution in a trench. When the thickness of the overburden is less than half of the trench depth, for a trench with the aspect ratio of unity, the microstructure in the trench tends to evolve into a bamboo structure. This effect is discussed in terms of grain sizes in the trench and those in the overburden. The thinner overburden layer would have smaller grains, of which growth is limited by its thickness. Such small-sized grains in the overburden are not likely to grow into the trench, which hardly make grain boundaries in the trench. Meanwhile, the grains from the trench are able to continue growth inside the trench, resulting in a bamboo structure. Overburden thickness affects the reliability and the electrical performance of the damascene copper interconnects. Optimization of overburden thickness is required to minimize these effects.     

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50 kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200 mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50 nm.     

Electromigration failure in ultra-fine copper interconnects

This paper presents experimental evidence suggesting that electromigration (EM) can be a serious reliability threat when the dimension of Cu interconnects approaches the nanoscale range. To understand the failure mechanism prevailing in nanoscale Cu interconnects, single-level, 400-μm long interconnects with various effective widths, ranging from 750 nm to 80 nm, were made, EM tested, and characterized in this investigation. The results indicate that interface EM (Cu/barrier) may be the predominant EM mechanism in all line widths. The evidence supporting the active Cu/barrier interface EM includes the fact that the EM lifetime is inversely proportional to the interface area fraction. Microscopic analysis of the failure sites also supports the conclusion of interface EM because voids and hillocks are found at the ends of the test strip, which is not possible if lines fail by grain-boundary EM in the test structure used in this study. In addition, our study finds evidence that failure is assisted by a secondary mechanism. The influence of this factor is particularly significant when the feature size is small, resulting in more uniform distribution of failure time in narrower lines. Although limited, evidence suggests that the secondary factor is probably attributed to pre-existing defects or grain boundaries.     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.     

Annealing kinetics and embrittlement of electrodeposited copper

Two types of 35 μm thick free-standing copper electrodeposits, one amenable to rapid annealing and the other responding sluggishly to thermal exposure, have been subjected to isothermal anneals at 100–250°C for up to 200 min. The apparent activation energy calculations from changes in mechanical properties yield 8.2 k cals/g atom for a “recovery” anneal of foil (i), and 15 k cals/g atom for a “recrystallization” anneal of foil (ii). This is in keeping with the values available in the literature for the electro and vapor deposits. Further, the electrodeposits display embrittlement, that is loss of ductility, at elevated temperature (180°C). The annealing gradually removes embrittlement, the removal rate depends upon the time/temperature parameters of the thermal exposure.     

Residual stress estimation in damascene copper interconnects using embedded sensors

Mechanical stress in damascene copper/low-k interconnects has been studied by means of micro-rotating sensors embedded in chips and directly integrated in CMOS process flow. A new hinge sensor design has been elaborated and a new analytical model of the mechanical equilibrium of sensors is validated. These sensors allow the study of the average residual stress as a function of the line width in a range from few hundred nanometers to several microns. It was found that the residual stress increases from 290 to 850 MPa in, respectively, 2 and 0.25 μm wide lines. This trend shows a yield stress increase with the line width reduction. Copper grains microstructure change between large and narrow lines is probably one of the reasons for yield stress and so residual stress increase. This microstructure change has been observed by means of Transmission Electron Microscopy (TEM) observations.     

Analysis and optimization of shielded RLC global interconnects for gigascale integration

Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes.     

Local textures and grain boundaries in voided copper interconnects

We have characterized grain boundary structures and local textures in stress voided copper lines. Grain boundary misorientations as well as the tilt and twist character of boundaries were measured using electron backscatter diffraction in the scanning electron microscope in conjunction with focused ion beam images. We have summarized data for a number of boundaries immediately adjacent to voids and made comparisons to boundaries from regions that remained intact. These data were acquired from the same lines, and so represent measurements from material with identical histories. Significant local variations in microstructure were observed. Local <111> textures of grains near voids were of lower strength than those away from voids. Grain boundaries intersecting voids were of higher angle character and had significant twist components. These results suggest that local regions associated with more favorable kinetics are more susceptible to void formation and growth.     

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.     

Electromigration characterization of damascene copper interconnects using normally and highly accelerated tests

We have completed a set of experiments on damascene Chemical Vapor Deposition Copper (CVD-Cu) interconnects using Wafer Level and Package Level Reliability (WLR and PLR) tests. Two line widths have been extensively characterized : W=4 and 0.6 μm. For both line widths, the activation energy values extracted using WLR and PLR data are good in agreement demonstrating that the active diffusion paths remain the same over the wide range of used measurement conditions : Ea=0.65eV for W = 4μm, Ea = 0.7-0.8eV for W = 0.6μm. spite of Ea experimental values lower than the reference values of the literature.     

Polymer residue chemical composition analysis and its effect on via contact resistance in dual damascene copper interconnects process integration

During via and trench plasma etching in dual damascene copper interconnects process integration, polymer residues and copper damage were created as by-products of the dry-etch process. The polymer residue chemical composition and copper damage were analyzed by Auger electron spectroscopy. Analysis result indicated that besides copper, carbon, oxygen, and nitrogen and trace amounts of chlorine and sulphur were also observed. The polymer residue and copper damage are the important reasons of cause higher via contact resistance and lower via yield. It could be reduced and eliminated effectively using optimized plasma etch recipe, improved polymer residue removal methods and improved pre-treatment before metal deposition and so on.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

Grain nucleation and texture analysis of electroless copper deposition on a palladium seed layer

Electroless copper grains were deposited on a Pd seed layer under varying bath conditions. The seed layer was determined to have a (111) texture using grazing incident x-ray (GIX) diffraction. Multiple nucleation sites in the grain boundaries were imaged using a scanning tunneling microscope. Continual copper growth produced row-like structures. The texture of the electrolessly deposited copper (ED-Cu) grains were determined to be (111). No radial grain orientation for the Pd seed layer or the ED-Cu thin film was detected using GIX diffraction. Atomic force microscope images indicated continual Cu nucleation throughout the deposition process. PdH was formed as a by-product of the electroless deposition process, and detected by x-ray diffraction.     

Fatigue of damascene copper lines under cyclic electrical loading

Fatigue in damascene copper lines has been investigated by using alternating currents to generate cyclic temperatures and stresses/strains. Interconnects using beyond 65 nm node design rules and materials have been studied. We demonstrate here that cyclic thermal strains lead to Cu or Cu/Co-based cap surface modification and open circuits in Cu lines during the application of an alternating electrical current. We underline that the narrower the copper lines are, the more reliable they are and the major role of the cap layer to improve the Cu lines reliability.     

Impact of process steps on electrical and electromigration performances of copper interconnects in damascene architecture

The impact of IC fabrication process steps on electrical and reliability characteristics of dual damascene copper interconnects has been analyzed. It is demonstrated that thermal treatments could have a negative impact on electrical performances unless a suitable encapsulation step of copper lines is performed. Electromigration performances are also strongly affected by annealing and the role that impurities have in dominating the diffusion paths is evidenced by experiments on differently fabricated copper structures of various widths.