Relating statistical MOSFET model parameter variabilities to ICmanufacturing process fluctuations enabling realistic worst case design

The implementation of a viable statistical circuit design methodology requiring detailed knowledge of the variabilities of, and correlations among, the circuit simulator model parameters utilized by designers, and the determination of the important relationships between these CAD model parameter variabilities and the process variabilities causing them is presented. This work addresses the above requirements by detailing a new framework which was adopted for a 2-μm CMOS technology to enable realistic statistical circuit performance prediction prior to manufacture. Issues relating to MOSFET modeling, the derivation of fast “direct” parameter extraction methodologies suitable for rapid parameter generation, the employment of multivariate statistical techniques to analyze statistical parametric data, and the linking of the CAD model parameter variations to variabilities in process quantities are discussed. In this approach the correlated set of model parameters is reduced to a smaller and more manageable set of uncorrelated process-related factors. The ensuing construction and validation of realistic statistical circuit performance procedures is also discussed. Comparisons between measured and simulated variabilities of device characteristics is utilized to demonstrate the accuracy of the techniques described. The advantages of the proposed approach over more traditional “worst case” design methodologies are demonstrated     

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.     

Wavelet-Based Transistor Parameter Estimation

In this paper a wavelet-based parameter estimation method has been proposed for the common emitter transistor amplifier circuit and compared with the least squares method. As the maximal precision of simulation requires the modeling of electronic circuits in terms of device parameters and circuit components, the Volterra model of the common emitter amplifier circuit derived using the Ebers–Moll model and perturbation technique has been used for parameter estimation. The advantage of the proposed method is a smaller data storage requirement and accurate parameter estimation as compared to the least squares method because the wavelet method is adapted to time-frequency resolution.     

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.     

SPICE modeling of process variation using location depth corner models

For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

Realistic statistical worst-case simulations of VLSI circuits

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of VLSI circuits. Gradient analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2 μm 64 K CMOS static RAMs (SRAMs),     

Physics-based minority charge and transit time modeling for bipolartransistors

It has been well known for many years that the transit time model used in the SPICE Gummel-Poon model (SGPM) is not adequate for reliable design of circuits operating either at high current densities (including quasi-saturation), which is often the case in high-speed integrated circuits, or at low voltages, which is important for low-power applications. In addition, extraction of the SGPM's transit time model parameters is often very difficult and time consuming. Although various proposals for modeling the transit time were published in the past, most of them are not suited for compact transistor models required in circuit simulation from a numerical, parameter extraction and lateral scaling point of view. In this paper, a set of minority charge and transit time equations is derived which are physics-based and laterally scaleable as well as suitable for incorporation into compact models. Experimental results of the new model are presented in terms of transit time and transit frequency versus bias (I_C, V_CE), geometry, and temperature, showing excellent agreement for different types of silicon homojunction bipolar transistors     

Investigation of very fast and high-current transients in digitalbipolar IC's using both a new compact model and a device simulator

The design and optimization of high-speed integrated bipolar circuits requires accurate and physical transistor models. For this, an improved version of the compact model HICUM was developed. It is an extension of the small-signal model recently described to the large-signal (transient) case. The model, which takes into account emitter periphery and non-quasi-static (NQS) effects, is semi-physical, allowing the calculation of its elements for arbitrary transistor geometries from specific electrical and technological data. This is an important precondition for transistor optimization in a circuit and for worst case analysis. The model was verified for basic building blocks of high-speed digital circuits like emitter follower and current switch. For this, mixed-mode device/circuit simulation is used instead of measurements, since the latter would give too large errors for the fast transients of interest. It is demonstrated that-in contrast to the obsolete but frequently used SPICE Gummel/Poon model-the new HICUM is well suited for modeling very-high-speed transistor operation also at high current densities. Moreover, it is shown that at very fast transients the influence of NQS effects can no longer be neglected. As a practical application example, a high-speed E²CL circuit is simulated using the new model. The results show again that high-current models are very useful for designing IC's at maximum operating speed. This is because the optimum emitter size is often the minimum size, which is limited by high-current effects. Especially, in the case of current spikes (e.g., in emitter followers) it is difficult to find the optimum emitter size without having adequate transistor models     

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models

Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are difficult to obtain if the behavioral model is not accurate enough. Therefore, this paper proposes to use an efficient bottom-up approach to generate accurate process-variation-aware behavioral models of CPPLL circuits. Without blind regressions, only one input pattern in the extraction mode sufficiently obtains all required parameters in the behavioral model. A quasi-SA approach is also proposed to accurately reflect process variation effects. Considering generic circuit behaviors, the quasi-SA approach saves considerable simulation time for complicated curve fitting but still keeps estimation accuracy. The experimental results demonstrate that the proposed bottom-up modeling flow and quasi-SA equations provide similar accuracy as in the RSM approach, using less extraction cost as in the traditional sensitivity analysis approach.      

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

一类时序逻辑电路的逻辑参数提取 激励波形自动生成

提出了对具有反馈信息的时序逻辑电路进行逻辑参数提取时用于SPICE模拟的激励波形自动生成方法,该方法能根据用户指定的要提取的时延参数要求,很快产生这种时序逻辑电路的模拟激励波形,从而可以加快逻辑参数的提取过程,保证参数提取激励波形的正确性．该方法的实现,可以使逻辑参数的提取完全自动化,缩短了逻辑参数库的建立时间,具有较高的适用价值．     

实用线性IC电路模拟系统的开发

本文介绍了可广泛用于IC电路设计的线性IC电路模拟系统。主要叙述了电路模拟软件实用功能设计,新的器件模型的建立;叙述了把电路模拟与实际工艺结合起来的参数提取程序的设计。     

An automatic parameter extraction technique for advanced CMOS device modeling using genetic algorithm

We in this paper present an computational intelligence technique to extract semiconductor device model parameters. This solution methodology is based on a genetic algorithm (GA) with an exponential type weight function, renew operator, and adaptive sampling scheme. The proposed approach automatically extracts a set of complete parameters with respect to a specified compact model, such as a BSIM model for deep-submicron and nanoscale complementary metal-oxide-semiconductor (CMOS) devices. Compared with conventional artificial step-by-step fitting approaches, the proposed extraction methodology automatically tracks the shape variation of current-voltage (I-V) curves and examines the first derivative of I-V curves; therefore, highly accurate results can be obtained directly. Applying the renew operator will keep the evolutionary trend improving by removing the individuals without mainly features. The sampling strategy will speed up the evolution process and still maintain the extraction accuracy in a reasonable range. A developed prototype is successfully applied to extract model parameter of N- and P-metal-oxide-semiconductor field effect transistors (MOSFETs). This optimization method shows good physical accuracy and computational performance, and provides an alternative for optimal device modeling and circuit design in nanodevice era. Genetic algorithm based automatic model parameter extraction bridges the communities between circuit design and chip fabrication; in particular, it will significantly benefits design of system-on-a-chip.     

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.     

An efficient algorithm for the extraction of parameters with high confidence from nonlinear models

Analytical models with parameters numerically extracted from I-V data have been used in simulation of MOS circuits. The equations are quasi-physical and the extracted parameters do not normally relate to any single identifiable physical mechanism. We have developed an extraction system that can provide a measure of the level of confidence in the extracted parameters; hence, these parameters may be reliably used in circuit simulation as well as process control. The algorithm described is model independent and can be used for any nonlinear least-squares parameter extraction problem.     

片上螺旋变压器等效电路参数的直接提取

本文比较了四端口和两端口测试方式下变压器模型的差异。虽然两端口测试方式对变压器的测试和应用更为合适,但它将给模型参数的提取带来巨大困难。在这篇文章中,一种基于物理意义的等效电路模型和它相应的直接提取步骤被提出来用于片上变压器。基于两端口（而非四端口）测试方式,这种参数提取步骤能够提取器件的模型参数而不需要使用任何参数优化和拟合。在这个步骤中,一个新方法首次被提出用来提取阶梯电路的参数,而阶梯电路被广泛用于模拟各种无源器件中的趋肤效应。这样,这个方法便可以推广应用到其他无源器件的建模中,如片上传输线、电感、巴伦等。为了检验这种参数提取步骤的有效性和准确性,我们用90-nm 1P9M CMOS工艺制作了一个片上互绕型变压器。我们比较了模型仿真和实际测试在自感、品质因数、感性互感系数和阻性互感系数等方面的结果,在很宽的频带宽度内这两者吻合得很好。     

Extraction error modeling and automated model debugging in high-performance custom designs

In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of design representation may not be appropriate for test generation tools that usually require a model expressed at the gate level. Logic extraction is a key step in test model generation to produce a gate-level netlist from the transistor-level representation. This is a semi-automated process which is error-prone. Once a test model is found to be erroneous, manual debugging is required, which is a resource-intensive and time-consuming process. This paper presents an in-depth analysis of typical sets of extraction errors found in the test model representations of the pipelines in high-performance designs today. It also develops an automated debugging solution for single extraction errors for pipelines with no state equivalence information. A suite of experiments on circuits with similar architecture to that found in the industry confirms the fitness and practicality of the solution.