退火气氛对Ge MOS电容电特性的影响

采用反应磁控溅射法在Ge衬底上制备了HfTiO高介电常数k栅介质薄膜,研究了不同气体(N2、NO、N2O)淀积后退火对Ge金属-氧化物-半导体(MOS)电容性能的影响.透射电子显微镜和电特性测量表明,湿N2退火能有效抑制界面层的生长,提高界面质量,改善栅极漏电流特性,从而得到最优的器件性能,即Al/HfTiO/n-Ge MOS电容的栅介质等效氧化物厚0.81 nm,k=34.5,带隙中央界面态密度为2.4×1011cm-2·eV-1,1 V栅偏压下的栅极漏电流为2.71×10-4A·cm-2.     

HfTiO高k栅介质Ge MOS电容的制备及特性分析

采用反应磁控溅射方法和湿氮退火工艺在Ge衬底上分别制备了HfO2和HfTiO高介电常数(k)栅介质薄膜。电特性测量表明,HfTiO样品由于Ti元素的引入有效提高了栅介质的介电常数,减小了等效氧化物厚度,但同时也使界面态密度有所增加。控制HfTiO中Ti的含量及表面预处理工艺有望改善HfTiO/Ge界面质量。     

HfTiO高κ栅介质Ge MOS电容特性研究

采用反应磁控共溅射方法在Ge衬底上制备亚-nm等效氧化物厚度(EOT)的HfTiO高κ栅介质薄膜,研究了湿N2和干N2气氛退火对GeMOS电容电特性的影响。隧穿电子显微镜、椭偏仪、X射线光电子频谱、原子力显微镜以及电特性的测量结果分别表明,与干N2退火比较,湿N2退火能明显抑制不稳定的低κGeOx界面层的生长,从而减小栅介质厚度,降低栅介质表面粗糙度,有效提高介电常数,改善界面质量和栅极漏电流特性,这都归因于GeOx的易水解性。还研究了Ti靶溅射功率对HfTiO栅介质GeMOS器件性能的影响。     

Al掺杂HfO2高k栅介质沉积后退火工艺研究

为满足集成电路发展需求,通过向HfO2掺入Al元素形成Al掺杂的HfO2新型高k材料,并在不同的环境和温度下进行退火,研究其电学特性的变化。通过对电学参数的分析,研究Al掺杂HfO2材料体内正电荷缺陷、k值（晶相变化）、界面层厚度、栅漏电等的影响。最终,在N2环境中700℃退火条件下,Al掺杂HfO2的电学特性达到最优,其EOT为0.88nm、Vfb为0.46V和Ig为2.19×10-4A/cm2。最优条件下的EOT可以满足14/16nm器件的需要（EOT<1nm）,Ig比相同EOT的HfO2材料小3个数量级。     

超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

表面预处理对Ge MOS电容特性的影响

通过不同气体(NO、N2O、NH3)对Ge衬底进行表面预处理,生长GeOxNy界面层,然后采用反应磁控溅射方法生长HfTiO薄膜,制备HfTiO/GeOxNy叠层高k栅介质Ge MOS电容,研究表面预处理对界面层以及界面层对器件性能的影响.隧穿电子扫描电镜(TEM)、栅电容-电压(C-V)栅极漏电流-电压(J-V)的测量结果表明,湿NO表面预处理能生长高质量的界面层,降低界面态密度,抑制MOS电容的栅极漏电流密度.施加高场应力后,湿NO表面预处理样品的平带漂移及漏电流增加最小,表示器件的可靠性得到有效增强.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高 3nm栅氧 W/ Ti N叠层栅 MOS电容的性能 .实验选取了合适的 Ti N厚度来减小应力 ,以较小的 Ti N溅射率避免溅射过程对栅介质的损伤 ,并采用了较高的 N2 / Ar比率在 Ti N溅射过程中进一步氮化了栅介质 .实验得到了高质量的 C- V曲线 ,并成功地把 Nss(表面态密度 )降低到了 8× 10 1 0 / cm2以下 ,达到了与多晶硅栅 MOS电容相当的水平     

高k HfO2栅介质淀积后退火工艺研究

研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求.     

不同温度退火的HfTiON栅介质MOS电容电特性研究

在N2/O2气氛中,使用Ti、Hf靶共反应溅射在衬底Si上淀积一种新型栅介质材料HfTiON,随后分别在N2气氛中600°C和800°C退火2min。电容电压(C-V)特性和栅极漏电流特性测试结果表明,800°C快速热退火(RTA)样品表现出更低的界面态密度、更低的氧化物电荷密度和更好的器件可靠性,这是由于在800°C下的RTA能有效地消除溅射生长过程中导致的损伤,形成高质量、高可靠性的介质/Si界面。     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

YON界面钝化层改善HfO2/Ge界面特性的研究

本文采用YON界面钝化层来改善HfO₂栅介质Ge metal-oxide-semiconductor（MOS）器件的界面质量和电特性.比较研究了两种不同的YON制备方法：在Ar+N₂氛围中溅射Y₂O₃靶直接淀积获得以及先在Ar+N₂氛围中溅射Y靶淀积YN再于含氧氛围中退火形成YON.实验结果及XPS的分析表明,后者可以利用YN在退火过程中先于Ge表面吸收从界面扩散的O而氧化,从而阻挡了O扩散到达Ge表面,更有效抑制了界面处Ge氧化物的形成,获得了更优良的界面特性和电特性：较小的CET（1.66 nm）,较大的k值（18.8）,较低的界面态密度（7.79×10¹¹ eV^-1cm^-2）和等效氧化物电荷密度（-4.83×10¹² cm^-2）,低的栅极漏电流（3.40×10^-4 A/cm²@V_g=V_fb+1 V）以及好的高场应力可靠性.     

HfO2/TaON叠层栅介质Ge MOS器件制备及电性能研究

为提高高k/Ge MOS器件的界面质量,减小等效氧化物厚度(EOT),在high-k介质和Ge表面引入薄的TaON界面层.相对于没有界面层的样品,HfO2/TaON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和较好的输出特性.因此利用TaON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的高k/Ge界面质量有着重要的意义.     

Investigation on interracial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH3-plasma treatment procedures on interracial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated.The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric,i.e.before or after interlayer (TaON)deposition,or after deposition ofhigh-k dielectric (HfTiON).It was found that the excellent interface quality with an interface-state density of 4.79 × 1011 eV-1cm-2 and low gate leakage current (3.43 × 10-5 A/cm2 at Vg =1 V) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition.The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds,i.e.more GeOxNy,which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeOx interfacial layer,and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.