Large area MOS-gated power devices using fusible link technology

A new approach for improving the yield of large area MOS-gated power devices is described based upon wafer repair using fusible links of aluminum or polysilicon to isolate defective segments from the rest of the device. Unlike previously reported wafer repair techniques, the proposed approach does not require any knowledge of the location of the fault (gate-to-source short) within the device. Work done on the development of power-MOS process compatible fusible links is described in this paper. Power MOSFET's and IGBT's have been successfully fabricated using these fusible links to perform wafer repair     

Accurate estimation of statistical parametric variation in microelectronic test structures

Advanced technologies of microelectronic device fabrication need accurate determination of process parameters and their analysis. Test structures which represent individual process steps are incorporated in the design. Independent measurements can be carried out on these structures and the information is used as a feedback in order to achieve perfection at different stages of fabrication. This note presents an algorithm for analysis of measurement data and identification of defective sites on the wafer leading to an accurate yield analysis.     

Yield modeling of acoustic charge transport transversal filters

This paper presents a yield model for acoustic charge transport transversal filters. This model differs from previous IC yield models in that it does not assume that individual failures of the nondestructive sensing taps necessarily cause a device failure. A redundancy in the number of taps included in the design is explained. Poisson statistics are used to describe the tap failures, weighted over a uniform defect density distribution. A representative design example is presented. The minimum number of taps needed to realize the filter is calculated, and tap weights for various numbers of redundant taps are calculated. The critical area for device failure is calculated for each level of redundancy. Yield is predicted for a range of defect densities and redundancies. To verify the model, a Monte Carlo simulation is performed on an equivalent circuit model of the device. The results of the yield model are then compared to the Monte Carlo simulation. Better than 95% agreement was obtained for the Poisson model with redundant taps ranging from 30% to 150% over the minimum     

Dynamic Self‐Repair Architectures for Defective Through‐silicon Vias

Three‐dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through‐silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built‐in self‐test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self‐repair architectures using code‐based and hardware‐mapping based repair.     

Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB?

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by fabrication errors. The fraction of defective chips that escapes to the customer is called the defect level, also known as defective parts per million (DPPM, or simply PPM) when normalized to one million units. This paper demonstrates a technique used to correlate coverage goals to DPPM based on test fallout data using a MATLAB^?-based error function minimization approach. This analysis is explained using regression models for DPPM yield versus fault/defect coverage. This approach is beneficial to semiconductor companies for calibrating their fault coverage goals to meet DPPM requirements from automotive or other customers that have very aggressive (i.e., ultra-low) DPPM demands.     

Improving quality: Yield versus test coverage

Until now, it has been thought that the best way to improve quality was to improve yield, that is, to improve the manufacturing process so that fewer defective parts are manufactured. This philosophy has been applied to all areas of manufacturing, from widgets to whalers. One of the tenets of this philosophy is that quality should not be tested in, but should be built in via a well-controlled process that is continuously improving. However, when it comes to semiconductors, significant improvements for a process in order to improve yields can cost millions of dollars. In such a capital intensive industry, where the life of a process is only a few years, such investments are often not in the best economic interests of a semiconductor manufacturer. How, then, can the customers' requirements for quality be met? This article shows that for typical values of yield and test coverage, quality improves faster due to improvements in test coverage than it does for improvements in yield. As a result, testing can be used to achieve improvements in quality at lower costs, and therefore more economically, than improvements in the manufacturing process.     

A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology

Chemically assembled electronic nanotechnology (CAEN) is under intense investigation as a possible alternative or complement to CMOS-based computing. CAEN is a form of molecular electronics that uses directed self-assembly and self-alignment to construct electronic circuits from nanometer-scale devices that exploit quantum-mechanical effects. Although expected to have densities greater than 10⁸ gate-equivalents/cm², CAEN-based systems may possibly exhibit defect densities of up to 10%. The highly defective CAEN circuits will therefore require a completely new approach to manufacturing computational devices. In order to achieve any level of significant yield, it will no longer be possible to discard a device once a defect is found. Instead, a method of using defective chips must be devised. A testing strategy is developed for chemically assembled electronic nanotechnology (CAEN) that takes advantage of reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This strategy is particularly suited for regular architectures with high defect densities.     

Noncompressible Hemostasis and Bone Regeneration Induced by an Absorbable Bioadhesive Self-Healing Hydrogel

Bone bleeding and bone defects arising from trauma or bone tumor resection pose a great threat to patients and they are challenging problems to orthopedic surgeons. Traditional hemostatic materials are not suitable for bone fractures where compression cannot be applied, neither are they effective during surgeries where large amounts of body fluids prevent them from adhering to the large and irregular bone wound sites. This research introduces a catechol-conjugated chitosan (CHI-C) multi-functional hydrogel with adhesion, self-healing, cytocompatibility, hemocompatibility, and blood cell coagulation capacity. The hydrogel can be injected into internal and irregular bleeding sites and bone defective areas, and then rapidly self-heals (within 2 min) to an integrated hydrogel that fully fills the defective sites and strongly sticks to bleeding areas in the presence of body fluids during surgery. In vivo experiments using a rabbit ilium bone defect model demonstrate quick hemostasis after the hydrogel is applied and the blood loss is only ¼ compared to the untreated injuries. In addition, the bone regeneration is not interfered by the hydrogel and the bone defect is no longer visible with disappearance of the hydrogel after 4 weeks. This multi-functional hydrogel is potentially valuable for clinical applications towards tissue adhesion, hemostasis, and bone regeneration.     

Defect size variations and their effect on the critical area of VLSI devices

The effect on VLSI device yield of variations in the size of defects has not been widely recognized until recently, when the theory of critical areas and fault probabilities was developed. It is shown that assumptions regarding the defect size distribution can substantially affect the computed critical area.     

Optimization of device area and overall delay for CMOS VLSI designs

This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.     

适合于改善金属接触孔清洗的单晶圆工艺

在半导体制造流程中,晶圆清洗正在成为一种更加关键的工序模块。因为集成度的提高,需制定适合于清洗机及更高器件结构均匀性的要求。清洗的有效性最终会影响器件的性能和成品率[1-4]。无论在生产线前端或后端清洗工艺中,正在受到越来越仔细检查。在金属化工艺之前,一个有意义的方面是刻蚀和灰化后期金属接触孔侧壁和底部残留物的清除。因其会导致器件失效,一种不完全接触孔清洗技术成为一种主要的业务。     

Modeling the critical area in yield forecasts

Semiconductor device yield is determined primarily by the defect density and the critical area, i.e., that portion of the circuit active area in which the occurrence of a defect results in yield loss. A mathematical theory is developed for fault probability and critical area in terms of device geometry and defect size distribution. Equations are derived for its computation for different geometries, and the physical significance of the parameters contained in the equations is discussed.     

Structural Test and Diagnosis for Graceful Degradation of NoC Switches

Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86?% and 72.42?% of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.     

Critical area extraction for soft fault estimation

Algorithms are presented for extracting the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout. These algorithms have been implemented within the Edinburgh Yield Estimator (EYE) tool which permits efficient extraction of the critical area from an arbitrary mask layout. Accurate estimates of device critical area of even the largest devices can be obtained in a reasonable time using the sampling version of the tool. The application of these algorithms to defect related reliability is explored and results reported that compare the susceptibility to soft faults before and after layout modifications intended to enhance manufacturing yield. These results suggest that yield enhancement techniques can have a significant impact on defect-related device reliability     

Signal noise perturbation on automotive mixed-mode semiconductor device generated by graded substrate defect

The semiconductor technologies evolution allows greatly reducing noise impact on products and many structures have been created to reduce its effect. However, this paper presents the apparition of a noise issue during the production of a mixed-mode device dedicated to automotive applications. The research investigations concerned the fact that failure was not detected at test level but at customer level; therefore, it was determinant to understand the root cause of this failure mode to drive corrective actions in order to secure customer. The challenge was to analyse noise in Failure Analysis (FA) without fault spatial localization results. Indeed, Light Emission Microscopy (EMMI) and Thermal Laser Stimulation (ex: Soft Defect Localization – SDL) were unable to provide any defective area in the product. The lack of failing device identification led us to combine electrical and design analyses in order to define hypothesis on the failure origin. It was then possible to drive physical investigations through different approaches, using physical cross-section, Secondary Ion Mass Spectrometry (SIMS) and Scanning Capacitance Microscopy (SCM) techniques. Finally, the obtained complementary results will be discussed and an explanation of the failure mechanism will be presented as the root cause issue, allowing defining the defective step in production process.     

A Minimally Invasive Microdevice for Molecular Sampling and Analysis

In this paper, we present a new minimally invasive biopsy microdevice adapted to proteomic mass spectrometry analysis. The concept is born from a multidisciplinary collaboration in fields of proteomics, cancer research, and microtechnology. In mixing different skills, we have developed and manufactured a miniaturized biopsy device using microtechnology techniques in order to minimize tissue damage during surgical gesture. Dedicated chemically functionalized areas were added to the device in order to increase capture yield and specificity during tissue contact. Fields of application range from cancer research to the study of neurodegenerative diseases.      

Implicit deregistration in a PCS network

Registration/deregistration is required in a PCS network when a portable moves between registration areas. Several schemes were proposed to deregister a portable after it moves out of a registration area (RA). A simple scheme called implicit deregistration totally eliminates network traffic due to deregistration. However, this scheme may delete valid registration records. Thus, the size of a registration database must be sufficiently large to ensure low probability that a valid registration record is deleted. This paper describes an analytic model to determine the size k of the registration database for an RA in the implicit deregistration scheme. If the expected number of portables in an RA is N, then our study indicates that good performance can be achieved if k≃5N     

A simple method of photomask yield optimization by defect inspection

The quality of the photomask set decides to a large extent the quality and quantity of the device that will be produced. In order to ensure the quality of the photomasks, several sophisticated instruments are commercially available. However, in a research type of environment, the cost of such equipment can be prohibitive. In this paper, we propose a simple method of multiple master mask preparation with subsequent matching of defective die locations to optimize the master mask set. The advantage here is that a very good master mask set can be chosen so that minimum number of dies on the photomask set itself contribute to low wafer yield. The method is based on manual inspection of individual dies on photomasks and can be practically used for a complexity of up to 500 components.     

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.     

Microwave plasma devices—Promise and progress

Over the last few years, considerable effort has been devoted to employing the plasma state in applications as widely differing as microwave and optical frequency devices; power generation by thermonuclear fusion; magnetohydrodynamic (MHD) and thermionic energy conversion, and the propulsion of spacecraft. In some of these areas intense activity still continues, and encouraging progress is being made. In others the results have been disappointing, and after an initial period of enthusiasm interest has waned. This paper is restricted to such an area, and reviews microwave plasma device research. A few years ago it seemed that a new and useful range of components, including phase shifters, beam-plasma amplifiers, and harmonic generators, might be developed. After a great deal of work, there is still a dearth of serious commercial plasma competitors to existing vacuum tube and solid-state devices. The paper discusses some of the obstacles to microwave plasma device development that have been encountered along the way, and some of the paths that have been taken to circumvent them. It is concluded that the present disappointing situation is likely to persist unless a major breakthrough is made in production of a simple quiescent plasma source, or there is a departure from the present device concepts.